System for detachably mounting semiconductors on conductor substrate

• US 5,014,161 A
• Filed: 02/07/1990
• Issued: 05/07/1991
• Est. Priority Date: 07/22/1985
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Beck, Richard, Amdahl, Gene M., Lee, James C. K., Lee, Chune, Hu, Edward
• Primary Examiner(s): Pellinen, A. D.
• Assistant Examiner(s): Gaffin, Jeffrey A.
• Application Number:
  US07/477,133
• Time in Patent Office: 454 Days
• Field of Search: 361/386, 361/387, 361/388, 361/400, 361/403, 357/80, 357/81, 439/71
• US Class Current: 361/709
• CPC Class Codes: H01R 13/2414 conductive elastomers
• CPC Class Codes: H01R 43/007 for elastomeric connecting elements
• CPC Class Codes: H01R 43/16 for manufacturing contact members, e.g. by punching and by bending

Abstract

A semiconductor mounting system is provided for the detachable surface mounting of one or more semiconductor dies on a conductor substrate, such as a ceramic substrate or printed circuit board. The system employs a resilient, anisotropic conductor pad which is interposed between the semiconductor die and the conductor substrate. The conductor pad is capable of conducting electric signals in one direction only, and insulates in the other two orthogonal directions. Thus, by compressing the semiconductor die and resilient conductor pad against the conductor substrate, electrical contact is established between contacts on the semiconductor die and corresponding contacts on the conductor substrate. In the preferred embodiment, additional conductor pads are placed over the semiconductor dies, and a heat sink placed over the second conductor pads. In this way, the semiconductor dies are mounted in a resilient structure for protection, while heat dissipation is enhanced by the metallic elements in the second conductor pad.

Claims

1. A semiconductor die mounting system comprising:

a) a conductor substrate having an array of substrate contacts on a substrate face thereof;

b) at least one semiconductor die having first and second opposed die faces and a plurality of die contacts on the first die face thereof disposed in alignment with corresponding substrate contacts on the conductor substrate;

c) a conductor pad disposed between the substrate and the die having first and second opposed pad surfaces in contact with the substrate and first die faces, respectively, the conductor pad including a plurality of mutually electrically isolated electrically conductive elements extending between the first and second surfaces thereof in the direction of alignment between the substrate and die contacts so as to provide electrical conduction between the pad surfaces, adjacent conductive elements being spaced apart by less than the minimum width of the contacts; and

d) means for holding the semiconductor die and the conductor substrate in contact with the conductor pad so that the corresponding die and substrate contacts are in alignment.

2. A semiconductor die mounting system as in claim 1 wherein the means for holding the semiconductor die and the conductor pad includes a nest plate mounted over the conductor substrate for aligning the contacts on the conductor substrate with the contacts on the semiconductor die and a cover mounted on the nest plate.

3. A semiconductor die mounting system as in claim 2 wherein:

a) the cover includes a cover face; and

b) the semiconductor mounting system further includes a second conductor pad disposed between the semiconductor die and the cover, the second conductor pad having first and second opposed surfaces in contact with a cover face and the second die face, respectively, and including a plurality of thermally conductive elements extending between the first and second surfaces so as to provide thermal conduction between the die and the cover.

4. A semiconductor die mounting system as in claim 3 further comprising means for sealing the periphery of the cover to the periphery of the conductor substrate so that the semiconductor die and the conductor pads are compressed against the conductor substrate.

5. A semiconductor die mounting system as in claim 3 wherein the first-mentioned and second conductor pads are resilient.

6. A semiconductor die mounting system as in claim 2 wherein the cover is a heat sink.

7. A semiconductor die mounting system as in claim 1 wherein the conductor pad is resilient.

8. A semiconductor die mounting system as in claim 1 wherein the conductor substrate is a ceramic substrate.

9. A semiconductor die mounting system as in claim 1 wherein the substrate includes a pin grid on a face opposite the array of contacts.

10. A semiconductor die mounting system as in claim 1 wherein the substrate includes edge connectors formed about its periphery.

11. A semiconductor die mounting system as in claim 1 wherein the substrate includes a plurality of arrays of contacts formed on the substrate face and wherein a separate conductor pad is mounted on each array of contacts.

12. A semiconductor die mounting system comprising:

a) a conductor substrate having an array of substrate contacts on a substrate face thereof;

b) at least one semiconductor die having first and second opposed die faces and a plurality of die contacts on the first die face thereof disposed in alignment with corresponding substrate contacts on the conductor substrate;

c) a first conductor pad disposed between the substrate and the die having first and second opposed pad surfaces in contact with the substrate and first die faces, respectively, the conductor pad including a plurality of mutually electrically isolated electrically conductive elements extending between the first and second surfaces thereof in the direction of alignment between the substrate and die contacts so as to provide electrical conduction between the pad surfaces, adjacent conductive elements being spaced apart by less than the minimum width of the contacts;

d) means for holding the semiconductor die and the conductor substrate in contact with the first conductor pad so that the corresponding die and substrate contacts are in alignment;

e) a cover mounted on the means for holding the semiconductor die and the conductor substrate, the cover including a cover face; and

f) a second conductor pad disposed between the semiconductor die and the cover, the second conductor pad having first and second opposed surfaces in contact with a cover face and the second die face, respectively, and including a plurality of thermally conductive elements extending between the first and second surfaces so as to provide thermal conduction between the die and the cover.

13. A semiconductor die mounting system as in claim 12 wherein the means for holding the semiconductor die and the conductor pad includes a nest plate mounted over the conductor substrate for aligning the contacts on the conductor substrate with the contacts on the semiconductor die.

14. A semiconductor die mounting system as in claim 12 further comprising means for sealing the periphery of the cover to the periphery of the conductor substrate so that the semiconductor die and the conductor pads are compressed against the conductor substrate.

15. A semiconductor die mounting system as in claim 12 wherein the first and second conductor pads are resilient.

16. A semiconductor die mounting system as in claim 12 wherein the cover is a heat sink.

17. A semiconductor die mounting system comprising:

a) a conductor substrate having an array of substrate contacts on a substrate face thereof;

b) at least one semiconductor die having first and second opposed die faces and a plurality of die contacts on the first die face thereof disposed in alignment with corresponding substrate contacts on the conductor substrate;

c) a first conductor pad disposed between the substrate and the die having first and second opposed pad surfaces in contact with the substrate and first die faces, respectively, the conductor pad including a plurality of mutually electrically isolated electrically conductive elements extending between the first and second surfaces thereof in the direction of alignment between the substrate and die contacts so as to provide electrical conduction between the pad surfaces, adjacent conductive elements being spaced apart by less than the minimum width of the contacts;

d) a nest plate mounted over the conductor substrate for aligning the contacts on the conductor substrate with the contacts on the semiconductor die;

e) a cover having a cover face mounted on the nest plate; and

f) a second conductor pad disposed between the semiconductor die and the cover, the second conductor pad having first and second opposed surfaces in contact with a cover face and the second die face, respectively, and including a plurality of thermally conductive elements extending between the first and second surfaces so as to provide thermal conduction between the die and the cover.

18. A semiconductor die mounting system as in claim 17 further comprising means for sealing the periphery of the cover to the periphery of the conductor substrate so that the semiconductor die and the conductor pads are compressed against the conductor substrate.

19. A semiconductor die mounting system as in claim 17 wherein the first and second conductor pads are resilient.

20. A semiconductor die mounting system as in claim 17 wherein the cover is a heat sink.