Data-processing system having a packet transfer type input/output system

• US 5,014,186 A
• Filed: 09/27/1988
• Issued: 05/07/1991
• Est. Priority Date: 08/01/1986
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Chisholm, Douglas R.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Loomis, John C.
• Application Number:
  US07/250,996
• Time in Patent Office: 952 Days
• Field of Search: 364/200, 364/900
• US Class Current: 710/30
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: G06F 13/4018 with data-width conversion

Abstract

In a data processing system having a system bus for coupling I/O units to a system storage unit, there is provided a mechanism for supplying to the I/O units a line size signal representing the line size of the system storage unit. A further mechanism is located in at least one of the I/O units for responding to this line size signal for adjusting the data transfer size of the I/O unit to match the system storage unit line size.

Claims

1. In a data processing system having a system bus coupling I/O units which I/O units transmit data word packets to a system storage unit with a predetermined data work line size through a bus control unit for passing the data word packets between the storage system and the I/O units, the improvement comprising:

means for supplying to the I/O units a line size signal representing the data word line size of the system storage unit;

and means located in at least one of the I/O units and responsive to the data word line size signal for adjusting the data words per packet size of the I/O unit to match the system storage unit data word line size;

whereby the words per packet transferred from or to the I/O unit match the data word line size of the system storage unit.

2. The improvement of claim 1 wherein the line size signal is a plural-bit binary coded signal.

3. The improvement of claim 1 wherein the line size signal is supplied via separate dedicated signal conductors associated with the system bus.

4. The improvement of claim 1 wherein the line size signal is supplied via a status byte transferred over the system bus to the I/O control units.

5. In a data processing system having a system bus coupling I/O units to a system storage unit with a predetermined data word line size through a bus control unit for passing the data word packets between the storage system and the I/O units, the improvement comprising:

means for supplying a line size signal representing the data word line size of the system storage unit;

and means located in at least one of the I/O units for transferring a packet of time sequential data words to or from the system storage unit and responsive to the data word line size signal for adjusting the number of words in the packet to match the system storage unit line size with a predetermined data word line size through a bus control unit for passing the data word packets between the storage system and the I/O units.

6. An I/O unit for use in a data processing system having a system storage unit, a system bus for coupling I/O units to the system storage unit, a bus arbitration mechanism for receiving request signals from I/O units and supplying an acknowledgement signal to a selected I/O unit and means for supplying to I/O units a line size signal representing the line size of the system storage unit, such I/O unit comprising:

address register means for holding a system storage unit starting address;

buffer means for holding a plurality of data words;

bus request means for coupling to the system bus for requesting use of the bus by the I/O unit;

bus acknowledgement means for coupling to the system bus for receiving an acknowledgement signal granting use of the system bus to the I/O unit;

first logic means coupled to the address register means and to the buffer means and responsive to a received acknowledgement signal for causing a transfer of a starting address from the address register means to the system bus and for causing a sequential transfer of a plurality of data words between the system bus and the buffer means;

and second logic means coupled to the first logic means and responsive to the line size signal for limiting the member of data words transferred with the starting address so that the number of data words transferred does not exceed the line size of the system storage unit.

7. An I/O unit in accordance with claim 6 wherein the second logic means adjusts the number of data words transferred with the starting address so that the number of data words transferred matches the line size of the system storage unit.

8. A packet transfer type I/O unit which data is in word packets for use in a data processing system having a system storage unit with a predetermined data line size, a system bus for coupling the I/O units to the system storage unit through a bus control unit, a bus arbitration mechanism connected to the systems bus for receiving request signals from I/O units and supplying an acknowledgement signal to a selected I/O unit and means for supplying to I/O units a line size signal representing the line size of the system storage unit, such packet transfer type I/O unit comprising:

address register means for holding a system storage unit starting address;

buffer means for holding a plurality of data words;

bus request means for coupling to the system bus for requesting use of the bus by the I/O unit;

bus acknowledgement means for coupling to the system bus for receiving an acknowledgement signal granting use of the system bus to the I/O unit;

packet transfer control means coupled to the address register means and to the buffer means and responsive to each received acknowledgement signal for causing a transfer of a data packet between the I/O unit and the system storage unit, each such data packet being comprised of a system storage unit starting address field followed by a sequence of data words;

and packet size adjusting means coupled to the first logic means and responsive to the line size signal for adjusting the number of data words in each full packet to match the line size of the system storage unit.