Data processing system
First Claim
1. A digital data processing system comprising:
- (a) a watch-dog circuit, which circuit comprises;
(i) timer means; and
(ii) a reset signal input coupled to the timer means;
said watch-dog circuit generating;
(iii) an output signal when(A) a time interval between successive resets of said timer means exceed a predetermined length;
or(B) a reset signal is supplied to said reset signal input while a further signal is absent; and
(iv) the further signal, at time intervals which do not exceed said predetermined length; and
(b) a system program for;
(i) supplying a reset signal to said reset signal input, and thereby resetting the timer means, during each occurrence of said further signal; and
(ii) responding to said output signal by assuming a predetermined state, wherein said system is further for;
(iii) periodically testing for the presence of said further signal,(iv) responding to such presence being detected by supplying a reset signal to said reset signal input while said further signal is still present, and(v) performing program steps unrelated to the watchdog circuit between each detection of the presence of said further signal and the subsequent supply of the reset signal in response.
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Accused Products
Abstract
A data processing system includes a microcomputer (1) and a watchdog circuit arrangement which includes a clocked counter (17) having an output Qn which is coupled to a reset input (RST) of the microcomputer. In order to increase the kinds of microcomputer malfunctions to which the watchdog circuit responds, the microcomputer is programmed to repeatedly generate predetermined reset signal bytes within respective time windows, such time windows corresponding to periods during which a further output Qn-1 of the counter is logic "1". The reset signal byte supplied by the microcomputer is compared by a comparator (10) with the predetermined reset signal byte, which is supplied thereto by a switched multiplexor (13), and if they match the output signal from the comparator resets the counter. Each time this occurs the microcomputer strobes the watchdog circuit by applying its address to a further input (22, 46) thereof. If a reset signal byte should be supplied by the microcomputer outside a time window and/or if such signal byte is incorrect, the resulting signal level at the output of the comparator, which is stored in a flip-flop (15), actuates the watchdog circuit to produce an output signal which resets the microcomputer. The logic value of the Qn-1 signal from the counter is periodically ascertained by the microcomputer to determine the subsequent time window during which the next reset signal byte is to be generated.
34 Citations
15 Claims
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1. A digital data processing system comprising:
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(a) a watch-dog circuit, which circuit comprises; (i) timer means; and (ii) a reset signal input coupled to the timer means;
said watch-dog circuit generating;(iii) an output signal when (A) a time interval between successive resets of said timer means exceed a predetermined length;
or(B) a reset signal is supplied to said reset signal input while a further signal is absent; and (iv) the further signal, at time intervals which do not exceed said predetermined length; and (b) a system program for; (i) supplying a reset signal to said reset signal input, and thereby resetting the timer means, during each occurrence of said further signal; and (ii) responding to said output signal by assuming a predetermined state, wherein said system is further for; (iii) periodically testing for the presence of said further signal, (iv) responding to such presence being detected by supplying a reset signal to said reset signal input while said further signal is still present, and (v) performing program steps unrelated to the watchdog circuit between each detection of the presence of said further signal and the subsequent supply of the reset signal in response.
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2. A programmed digital data processing system comprising:
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(a) a watchdog circuit including (i) resettable timer means; (ii) a reset signal input for receiving successive reset signals to reset the timer means; and (iii) means for supplying an output signal when a time interval between successive reset signals exceeds a predetermined length; and (iv) means for supplying a further signal at intervals which do not exceed said predetermined length, the output signal supplying means also supplying the output signal when the reset signal input receives a reset signal while the further signal is absent; (b) means for periodically testing for the further signal; (c) means, responsive to the periodically testing means, for subsequently supplying a corresponding one of the successive reset signals while the further signal is still present, which corresponding one of the successive reset signals corresponds to a finding by the periodically testing means that the further signal is still present; (d) means for assuming a predetermined state in response to the output signal; and (e) means for enabling performance of program steps unrelated to the watchdog circuit between each detection of said further signal and the corresponding subsequent supply of a reset signal. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method for using a watchdog circuit, the method comprising the steps of:
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(a) initializing first and second flags (F1, F2) and a specific address (AD) of a RAM to respective initialized values; (b) executing program steps unrelated to the watchdog circuit; (c) testing whether an (n-1)th bit of an n-bit counter has reached a predetermined logic level; (d) changing the first flag to a respective changed value, upon a positive result of step (c); (e) executing further program steps unrelated to the watchdog circuit; (f) testing whether the first flag has the respective changed value of step (d); (g) upon a positive result of step (f); (I) writing contents of the specific address to the watchdog circuit; (II) setting the first flag back to the respective initialized value; and (III) setting the second flag to a respective changed value; (h) executing still further program steps unrelated to the watchdog circuit; (i) testing whether the second flag has the respective changed value of step (g) (III); and (j) upon a positive result of step (i); (I) complementing the contents of the specific address; and (II) setting the second flag back to the respective initial value.
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Specification