Circuit arrangement for providing power for an IC chip in a telephone subset

• US 5,014,308 A
• Filed: 02/05/1990
• Issued: 05/07/1991
• Est. Priority Date: 02/09/1989
• Status: Expired due to Fees

• Current Assignee: Alcatel NV (Nokia Corporation)
• Original Assignee: Alcatel NV (Nokia Corporation)
• Inventors: Fox, Ronald C. S.
• Primary Examiner(s): Dwyer, James L.
• Assistant Examiner(s): Shehata, M.
• Application Number:
  US07/475,175
• Time in Patent Office: 456 Days
• Field of Search: 379/412, 379/413, 379/387, 379/324
• US Class Current: 379/413
• CPC Class Codes: H04M 19/08 with current supply sources at the substations generating ringing current H04M19/04

Abstract

A battery-less telephone subset retains data in its processor memory with a storage capacitor which is kept charged by three controlled charge circuits which deliver power from the line to the capacitor under various line conditions and phone states. The first charge circuit charges the circuit initially, the second charge circuit then charges the capacitor (6.8 v) while all subsets remain on-hook (line voltage 50 v). When a second subset goes off-hook and the line voltage drops (to about 10 v), the capacitor is charged by the third charge circuit at a lower voltage (3.5 v) that is nevertheless sufficiently high to maintain the first subset'"'"'s on-hook functions. Preferably, the third circuit is controlled by the subset'"'"'s line switch control circuit, thereby minimizing the number of required components.

Claims

1. In a first telephone subset of the high voltage type incorporating line terminal means, at least one processor means having a power terminal means, and a controllable semiconductor line switch means, a circuit arrangement for providing power, derived from line current connected to the line terminal means, to said processor means when said first telephone subset is in an on-hook mode and voltage dropped across said line terminal means is either above a predetermined magnitude when a second high voltage subset connected across said line terminal means is in an on-hook mode, or is below said predetermined magnitude as a result of said second subset being in an off-hook mode, said circuit arrangement comprising:

a storage capacitor means coupled across said power terminal means of said processor means,

a first capacitor charging circuit for operating said line switch means for a short predetermined initial period when said subset is in the on-hook mode and connecting said line current via the operated line switch means to said storage capacitor means to initially charge said storage capacitor means to a first predetermined voltage,

a second capacitor charging circuit for thereafter maintaining the charge on said storage capacitor at said first predetermined voltage while said line switch means is no longer being operated and said first and second telephone subsets remain in the on-hook mode, by coupling said line current to said storage capacitor means independently of said line switch means, and

a third capacitor charging circuit which is coupled to said storage capacitor means only when said voltage dropped across the said line terminal means is below said predetermined magnitude as a result of the second subset being in its off-hook mode, said third capacitor charging means maintaining a charge of a second predetermined voltage, of less magnitude than said first predetermined voltage, across said storage capacitor means to power said processor means, while the first subset remains in its on-hook mode and the second subset remains in its off-hook mode.

2. A circuit arrangement as claimed in claim 1, wherein said first capacitor charging circuit includes a first semiconductor switch means a switching path of which is coupled to a control element of said controllable semiconductor line switch, and a control element of which is coupled to an output of said processor means at which is provided a signal for a short predetermined period to momentarily operate said first semiconductor switch means and connect line current to said capacitor storage means via a path including the so operated said line switch to charge said storage capacitor means to said first predetermined voltage.

3. A circuit arrangement as claimed in claim 2, wherein said path connecting said line current to said storage capacitor means further includes a serially connected diode and inductance.

4. A circuit arrangement as claimed in claim 1, wherein said second capacitor charging circuit includes a second semiconductor switch means a switching path of which is connected between said line terminal means and said storage capacitor means and a control element of which is coupled to said power terminal means of said processor means, whereby said second semicondutor switch means is rendered conducting when the charge on said storage capacitor means reaches said first predetermined voltage.

5. A circuit arrangement as claimed in claim 1, including a voltage regulator means having an input coupled to said storage capacitor means and an output coupled to said power terminal means, said voltage regulator'"'"'s characteristics being such that a substantially constant third predetermined voltage is provided at said output when the charge on said capacitor storage means is either of the first predetermined voltage or the second predetermined voltage.

6. A circuit arrangement as claimed in claim 5, wherein said voltage regulator means is a three terminal voltage regulator.

7. A circuit arrangement as claimed in claim 5, wherein said third capacitor charging circuit includes said first semicondutor switch means whose said switching path couples said line terminal means to said storage capacitor means, and whose control element is coupled to a voltage controlled device, said voltage controlled device being arranged to monitor the difference between a voltage on the input and the voltage on the output of said voltage regulator means and when said difference equals a fourth predetermined voltage, cause said first semiconductor switch means to conduct sufficient line current to maintain a charge of said second predetermined voltage on said storage capacitor means.

8. A circuit arrangement as claimed in claim 7, wherein said voltage controlled device comprises a third semiconductor switch means a switching path of which is coupled between the control element of said first semiconductor and the output of said voltage regulator means, and a control element of which is coupled to the input of said voltage regulator means, said third semiconductor switch means being rendered non-conducting when the difference between the voltage on the input and the voltage on the output of the voltage regulator means equals said fourth predetermined voltage.

9. A circuit arrangement as claimed in claim 8, wherein said switching path of said third semiconductor switch means is connected to the control element of said second semicondutor switch means, which is rendered non-conducting when said third semiconductor switch is non-conducting, the charge on said storage capacitor means being maintained by said third capacitor charging circuit.

10. A circuit arrangement as claimed in claim 2, wherein a voltage reference device is connected across said storage capacitor means.

11. A circuit arrangement as claimed in claim 10, wherein said voltage reference device is a zener diode.