Vertical power MOSFET having high withstand voltage and high switching speed

• US 5,016,066 A
• Filed: 03/31/1989
• Issued: 05/14/1991
• Est. Priority Date: 04/01/1988
• Status: Expired due to Term

• Current Assignee: NEC Electronics Corporation (Renesas Electronics Corporation)
• Original Assignee: NEC Corporation
• Inventors: Takahashi, Mitsuasa
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): NGO, NGAN V
• Application Number:
  US07/331,449
• Time in Patent Office: 774 Days
• Field of Search: 357/23.4, 357/23.8, 357/23.12, 357/23.14, 357/41, 357/52, 357/89
• US Class Current: 257/339
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/36 characterised by the concentration or distribution of impurities in the bulk material within semiconductor regions H01L29/06
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors

Abstract

In a vertical field effect transistor including a source electrode and a gate on the front surface of a semiconductor substrate having one conductivity type and a drain electrode on the back surface of the substrate, the semiconductor device of the present invention has the structure wherein a connection region of one conductivity type positioned between two channel forming base regions of the opposite conductivity type is formed by a semiconductor layer having a higher impurity concentration than the drain region of the one conductivity type, and the surface portion of the connection region which is connected to the channel has a lower impurity concentration than the connection region.

Claims

1. A semiconductor device comprising:

a semiconductor layer of a first conductivity type;

a plurality of base regions of a second conductivity type which is opposite to said first conductivity type, said plurality of base regions being formed in a main surface of said semiconductor layer;

a plurality of source regions of said first conductivity type formed in said plurality of base regions;

a plurality of gate electrodes formed above at least partial portions of said base regions with insulator films interposed between said gate electrodes and said base regions, said portions being positioning between said source regions and said semiconductor layer;

a first semiconductor region of said first conductivity type having an impurity concentration which is higher than an impurity concentration of said semiconductor layer;

a second semiconductor region of said first conductivity type having an impurity concentration which is lower than an impurity concentration of said first semiconductor region, said second semiconductor region being formed in said main surface of said first semiconductor layer between said plurality of base regions, said first semiconductor region being formed between said second semiconductor region and said semiconductor layer, and side walls of said first semiconductor region being in contact with said base regions;

a source electrode connected electrically and commonly to said plurality of source regions; and

a drain electrode electrically connected to a back surface of said semiconductor layer opposite to said main surface.

2. A semiconductor device as claimed in claim 1, wherein said gate electrodes are also formed above said second semiconductor region with said insulator films interposed between said gate electrodes and said second semiconductor regions.

3. A semiconductor device as claimed in claim 1, wherein said first semiconductor region is shallower than said base regions.

4. A semiconductor device as claimed in claim 1, wherein said first semiconductor region is deeper than said base regions.

5. A semiconductor device as claimed in claim 1, wherein said source regions and said base regions have an octagonal shape.

6. A semiconductor device as claimed in claim 1, wherein said second electrode is connected to said back surface of said semiconductor layer through another semiconductor layer having said first conductivity type and a higher impurity concentration than said semiconductor layer.

7. A semiconductor device as claimed in claim 2, wherein impurity concentration of said semiconductor layer is from 1×

10¹⁴ cm^-3 to 5×

10¹⁶ cm^-3, conductivity of said semiconductor layer being from 100 ohm-cm to 0.4 ohm-cm, conductivity of said first semiconductor region being from 1.5 times to 3 times as large as that of said semiconductor layer, and impurity concentration of said second semiconductor region being from one half to twice as large as that of said semiconductor layer.

8. A semiconductor device as claimed in claim 7, wherein conductivity of said first semiconductor region is twice as large as that of said semiconductor layer, impurity concentration of said second semiconductor region being from one half of to the same as that of said semiconductor layer.

9. A semiconductor device as claimed in claim 7, wherein depth of said second semiconductor region is greater than 0.1 μ

m and smaller than to one half of that of said first semiconductor region.

10. A vertical MOSFET comprising:

a drain region;

a plurality of base regions formed on a first surface of said drain region;

a plurality of source regions formed in said plurality of base regions, respectively;

a gate electrode formed above said first surface between said source regions with an insulator film interposed between said gate electrode and said first surface;

a first semiconductor region having an impurity concentration which is higher than an impurity concentration of said drain region and being the same conductivity type as that of said drain region;

a second semiconductor region formed in said first surface of said drain region between said base regions, said second semiconductor region having an impurity concentration which is lower than an impurity concentration of said first semiconductor region and being the same conductivity type as that of said drain region, said first semiconductor region being formed between said second semiconductor region and said drain region, and side walls of said first semiconductor region being in contact with said base regions;

a source electrode connected electrically and commonly to said plurality of source regions; and

a drain electrode connected electrically to a second surface of said drain region opposite to said first surface.

11. A vertical MOSFET as claimed in claim 10, wherein said source regions and said base regions have an octagonal shape.

12. A vertical MOSFET as claimed in claim 10, wherein impurity concentration of said drain region is from 1×

10¹⁴ cm^-3 to 5×

10¹⁶ cm^-3, conductivity of said drain region being from 100 ohm-cm to 0.4 ohm-cm, conductivity of said first semiconductor region being from 1.5 times to 3 times as large as that of said drain region, and impurity concentration of said second semiconductor region being from one half to twice as large as that of said drain region.

13. A vertical MOSFET as claimed in claim 12, wherein conductivity of said first semiconductor region is twice as large as that of said drain region, impurity concentration of said second semiconductor region being from one half of to the same as that of said drain region.