Lateral MOS controlled thyristor

• US 5,016,076 A
• Filed: 02/28/1990
• Issued: 05/14/1991
• Est. Priority Date: 02/28/1990
• Status: Expired due to Term

• Current Assignee: American Telephone & Telegraph Company (AT&T, Inc.)
• Original Assignee: AT&T, Inc.
• Inventors: Darwish, Mohamed N.
• Primary Examiner(s): James, Andrew J.
• Assistant Examiner(s): Nguyen, Viet Q.
• Application Number:
  US07/486,459
• Time in Patent Office: 440 Days
• Field of Search: 357/38, 357/39
• US Class Current: 257/133
• CPC Class Codes: H01L 29/7455 produced by an insulated gate structure
• CPC Class Codes: H01L 29/749 with turn-on by field effect

Abstract

A lateral MOS-controlled thyristor (MCT) structure using a single MOS gate for both turn-on and turn off. By eliminating a parasitic lateral PNP transistor through the addition of a high resistivity region surrounding one output terminal, and adding a DMOS transistor to a conventional thyristor structure, the maximum turn-off current limit is increased with lower forward voltage drop than that available in prior art lateral MCTs.

Claims

1. A lateral MOS controlled thyristor, having first and second output terminals and a gate, disposed in the major surface of a high-resistivity semiconductor epitaxial layer (20) of a first conductivity type, is characterized by:

first (11) and second (12) spaced-apart regions of a second conductivity type in the epitaxial layer and adjacent to a major surface thereof;

a third region (13) of the first conductivity type within the first region and adjacent to the major surface;

a fourth region (14) of the second conductivity type in contact with the second region, disposed in the epitaxial layer and adjacent to the major surface;

a rectifying contact (22_o, 15 or 22_R) with the second region; and

,

a conductive layer (17) overlaying and insulated from selected portions of the epitaxial layer and the first and fourth regions;

wherein the first and third regions are connected together to form the first output terminal, the rectifying contact forms the second output terminal, and the conductive layer forms the gate.

3. The thyristor as recited in claim 1, or 2 wherein the second region is completely within the fourth region.

4. The thyristor as recited in claim 1, or 2 wherein the second region (12) having an extended region (12'"'"') which contacts the epitaxial layer below the major surface.

5. The thyristor as recited in claim 1 or 2, further characterized by:

a sixth region (16) having a conductivity of the first type, disposed in the epitaxial layer adjacent to the major surface thereof, such that the first region (11) is between the sixth and fourth (14) regions; and

an additional conductive layer (19), overlying and insulated from selected portions of the epitaxial layer and the first region (11), and between the third region (13) and the sixth region (16);

wherein the first region (11) is electrically connected to the third region (13) and the conductive layer (17) is electrically connected to the additional conductive layer (19).

6. The thyristor as recited in claim 5, further characterized by:

a buried layer (21) under the epitaxial layer (20), substantially underlaying the thyristor, extending and electrically connected to the sixth region (16).

7. The thyristor as recited in claim 6, wherein the buried layer (21) is a semiconductor material having a conductivity of the first type.

8. The thyristor as recited in claim 1, wherein the resistivity of the second region is lower than that of the fourth region and the resistivity of the epitaxial layer is greater than the resistivity of all the regions.

2. A lateral MOS controlled thyristor, having first and second output terminals and a gate, disposed in the major surface of a high-resistivity semiconductor epitaxial layer (20) of a first conductivity type, is characterized by:

first (11) and second (12) spaced-apart regions of a second conductivity type in the epitaxial layer and adjacent to a major surface thereof;

a third region (13) of the first conductivity within the first region and adjacent to the major surface;

a fourth region (14) of the second conductivity type in contact with the second region, disposed in the epitaxial layer and adjacent to the major surface;

a rectifying contact being a metal conductor (22_R) forming a Schottky barrier rectifying contact with the second region;

a conductive layer (17) overlaying and insulated from selected portions of the epitaxial layer and the first and fourth regions;

wherein the first and third regions are connected together to form the first output terminal, the rectifying contact forms the second output terminal, and the conductive layer forms the gate.