Half toning pixel processor

• US 5,016,191 A
• Filed: 09/02/1988
• Issued: 05/14/1991
• Est. Priority Date: 09/02/1988
• Status: Expired due to Fees

• Current Assignee: Tektronix Incorporated (Fortive Corp.)
• Original Assignee: Tektronix Incorporated (Fortive Corp.)
• Inventors: Radochonski, Pierre A.
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Nguyen, Phu K.
• Application Number:
  US07/239,736
• Time in Patent Office: 984 Days
• Field of Search: 364/518, 364/521, 364/519, 340/706, 340/728, 358/75, 358/283, 358/284, 400/63, 400/83, 400/126, 346/1.1, 346/140 R
• US Class Current: 345/596
• CPC Class Codes: G06T 11/001 Texturing; Colouring; Generation of texture or colour inpainting G06T5/77

Abstract

A pixel processor converts data indicating origin, direction, length and intensity of each of a set of lines forming a picture into a half tone bit map on the picture. The pixel processor organizes the picture into an array of similar half tone cells, each half tone cell being a rectangular array of pixels, by storing adjustable data indicating the size of a half tone cell and a pixel intensity threshold level for each pixel of a half tone cell. When processing each line, the pixel processor reads pixel data words out of the bit map, each pixel data word including at least one bit corresponding to a pixel along the path of the line. For each such bit, the pixel processor determines the half tone cell position of the corresponding pixel, determines whether the pixel intensity threshold level assigned to that half tone cell position is lower than the intensity level of the line and sets the state of the bit accordingly. After suitably altering relevant bits of each pixel data word, the pixel processor writes the altered pixel data word back into the bit map memory.

Claims

1. For a pixel processing system including a bit map memory storing pixel data bits, each pixel data bit corresponding to a separate pixel of a half tone cell array forming a graphic design and controlling appearance in said graphic design of said pixel data bit'"'"'s corresponding pixel, a half tone pixel processor comprising:

means for storing object description data indicating intensity and positioning relative to said half tone cell array of a graphic object to be included in said graphic design;

addressable memory means for storing at various addresses pixel intensity threshold data corresponding to each pixel of a half tone cell and for reading out said pixel intensity threshold data when addressed;

addressing means for determining from said stored object description data an address within said addressable memory means of pixel intensity threshold data corresponding to a particular pixel of said half tone cell array spanned by said graphic object when said graphic object is included in said graphic design, said addressing means addressing said addressable memory means with the determined address such that said addressable memory means reads out pixel intensity threshold data corresponding to the particular pixel;

a comparator for comparing the intensity indicated by said object description data to the pixel intensity threshold data read out of said addressable memory means and producing an output bit indicating a result of the comparison; and

means for setting a state of a bit stored in said bit map memory corresponding to said particular pixel in response to a state of said output bit.

2. The pixel processor in accordance with claim 1 wherein said object is a line and wherein said object description data indicates an origin of said line within said half tone cell array, a direction of said line from said origin, and a number of pixels of said half tone cell array spanned by said line when said line is included in said graphic design.

3. The pixel processor in accordance with claim 1 wherein said addressing means comprises:

means for generating an X address value proportional to a horizontal position of said particular pixel within a half tone cell;

means for generating a Y address value proportional to a vertical position of said particular pixel within said half tone cell; and

means for combining said X and Y address values to produce an address for addressing said addressable memory means.

4. The pixel processor in accordance with claim 3 wherein said means for combining comprises means for adding said X and Y address values to produce said address for addressing said addressable memory means.

5. For a pixel processing system including a bit map memory storing pixel data words, each pixel data word comprising a plurality of bits, each bit of each pixel data word processing to a separate pixel of a half tone cell array forming a graphic design, each bit controlling appearance in said graphic design of said bit'"'"'s corresponding pixel, a half tone pixel processor comprising:

data storage means storing origin data indicating an origin pixel within said half tone cell array of a line to be included in said graphic design, storing length data indicating a number of pixels of said half tone cell array spanned by said line, storing direction data indicating a direction of said line from said origin pixel, and storing line intensity data indicating intensity of said line;

addressable memory means storing at various addresses pixel intensity threshold data corresponding to pixels of a half tone cell and reading out said pixel intensity threshold data when addressed;

addressing means for determining from said stored origin, length and direction data addresses within said addressable memory means of pixel intensity threshold data corresponding to particular pixels of said half tone cell array spanned by said line when said line is included in said graphic design, and for sequentially addressing said addressable memory means with the determined addresses such that said addressable memory means reads out a sequence of pixel intensity threshold data corresponding to the particular pixels;

a comparator for successively comparing the stored line intensity data to the sequence of pixel intensity threshold data read out of said addressable memory means and for producing a sequence of output bits, each successive output bit indicating a result of a successive comparison; and

means for reading out of said bit map memory and storing a first pixel data word comprising particular bits corresponding to said particular pixels, for setting states of said particular bits of said stored first pixel data word in accordance with states of said output bits thereby to produce a second pixel data word, and for writing said second pixel data word into said bit map memory in place of said first pixel data word.

6. The pixel processor in accordance with claim 5 wherein said addressing means comprises:

means for generating a sequence of X address values indicating horizontal positions of said particular pixels within a half tone cell;

means for generating a sequence of Y address values indicating vertical positions of said particular pixels within said half tone cell; and

means for combining said X and Y address values to produce a sequence of addresses for addressing said addressable memory means.

7. For a pixel processing system including a bit map memory storing pixel data bits, each pixel data bit corresponding to a separate pixel of a half tone cell array forming a graphic design and each pixel data bit controlling appearance in said graphic design of said pixel data bit'"'"'s corresponding pixel, each half tone cell comprising a rectangular pixel array of adjustable horizontal and vertical dimensions, a half tone pixel processor responsive to input origin data indicating an origin pixel within said half tone cell array of a line to be included in said graphic design, length data indicating a number of pixels of said half tone cell array spanned by said line, direction data indicating a direction of said line from said origin pixel, line intensity data indicating intensity of said line, and X and Y dimension data respectively indicating said horizontal and vertical dimensions, the half tone pixel processor comprising:

means for storing said input origin, length, direction, intensity, and X and Y dimension data;

addressable memory means storing at various addresses pixel intensity threshold data corresponding to each pixel of a half tone cell and reading out said pixel intensity threshold data when addressed;

addressing means for determining from said stored origin, length, direction and X and Y dimension data addresses within said addressable memory means of pixel intensity threshold data corresponding to particular pixels of said half tone cell array spanned by said line, and for successively addressing said addressable memory means with said addresses such that said addressable memory means successively reads out a sequence of pixel intensity threshold data corresponding to the particular pixels;

a comparator for successively comparing the stored line intensity data to the sequence of pixel intensity threshold data read out of said addressable memory means and for producing a sequence of output bits, each successive output bit indicating a result of a successive comparison; and

means for setting states of bits stored in said bit map memory corresponding to said particular pixels in response to states of said output bits.

8. The pixel processor in accordance with claim 7 wherein said addressing means comprises:

means for generating a sequence of X address values indicating horizontal positions of said particular pixels within half tone cell;

means for generating a sequence of Y address values indicating vertical positions of said particular pixels within said half tone cell; and

means for combining said X and Y address value sequences to produce a sequence of addresses for addressing said addressable memory means.

9. The pixel processor in accordance with claim 8 wherein said means for generating a sequence of Y address values comprises:

latching means for successively latching input addresses to produce said sequence of Y address values; and

logic means for generating said sequence of input address values to said latching means, each successive input address value being determined by a combination of said origin, length, direction and X and Y dimension data, and a Y address value produced by said latching means.

10. For a pixel processing system including a bit map memory storing pixel data bits, each pixel data bit corresponding to a separate pixel of a half tone cell array forming a graphic design and controlling appearance in said graphic design of said pixel data bit'"'"'s corresponding pixel, each half tone cell comprising a rectangular pixel array of adjustable horizontal and vertical dimensions, a half tone pixel processor responsive to input origin data indicating an origin pixel within said half tone cell array of a line to be included in said graphic design, length data indicating a number of pixels of said half tone cell array spanned by said line, direction data indicating a direction of said line from said origin pixel, line intensity data indicating intensity of said line, dimension data indicating horizontal and vertical dimensions of a half tone cell, and offset data indicating the adjustable offset of said half tone cell array, the half tone pixel processor comprising:

means for storing said input origin, length, direction, intensity, X and Y dimension and offset data;

addressable memory means for storing at various addresses input pixel intensity threshold data corresponding to each pixel of a half tone cell and for reading out said input pixel intensity threshold data when addressed;

addressing means for determining from said stored origin, length, direction, X and Y dimension and offset data addresses within said addressable memory means of pixel intensity threshold data corresponding to particular pixels of said half tone cell array spanned by said line, and for sequentially addressing said addressable memory means with the determined addresses such that said addressable memory means successively reads out a sequence of pixel intensity threshold data corresponding to the particular pixels;

a comparator for successively comparing the stored line intensity data to the sequence of pixel intensity threshold data read out of said addressable memory means and producing a sequence of output bits, each successive output bit indicating a result of a successive comparison; and

means for setting states of bits stored in said bit map memory corresponding to said particular pixels in response to states of said output bit.

11. For a pixel processing system including a bit map memory storing pixel data bits, each pixel data bit corresponding to a separate pixel of a half tone cell array forming a graphic design and each said data bit controlling appearance in said graphic design of said data bit'"'"'s corresponding pixel, a half tone pixel processing method comprising the steps of:

storing input object description data indicating intensity and positioning relative to said half tone cell array of a graphic object to be included in said graphic design;

storing at various addresses of an addressable memory means pixel intensity threshold data corresponding to each pixel of a half tone cell array.

determining from said stored object description data an address within said addressable memory means of pixel intensity threshold data corresponding to a particular pixel of said half tone cell array spanned by said graphic object when said graphic object is included in said graphic design;

addressing said addressable memory means with said address such that said addressable memory means read out said pixel intensity threshold data;

comparing the intensity indicated by said object description data to the pixel intensity threshold data read out of said addressable memory means and producing an output bit indicating a result of the comparison; and

setting a state of a bit stored in said bit map memory corresponding to said particular pixel in response to a state of said output bit.

12. The method in accordance with claim 11 wherein said object is a line and wherein said object description data indicates an origin of said line within said half tone cell array, a direction of said line from said origin, and a number of pixels of said half tone cell array spanned by said line when said line is included in said graphic design.

13. The method in accordance with claim 11 wherein the step of determining an address comprises the substeps of:

generating an X address value proportional to a horizontal position of said particular pixel within a half tone cell;

generating a Y address value proportional to a vertical position of said particular pixel within said half tone cell; and

adding said X and Y address values to produce said address.

14. For a pixel processing system including a bit map memory storing pixel data words, each pixel data word comprising a plurality of pixel data bits, each pixel data bit corresponding to a separate pixel of a half tone cell array forming a graphic design and each pixel data bit controlling appearance in said graphic design of said pixel data bit'"'"'s corresponding pixel, a half tone pixel processing method comprising the steps of:

storing origin data indicating an origin pixel within said half tone cell array of a line to be included in said graphic design;

storing length data indicating a number of pixels of said half tone cell array spanned by said line,

storing direction data indicating a direction of said line from said origin pixel,

storing line intensity data indicating intensity of said line;

storing at various addresses in an addressable memory pixel intensity threshold data corresponding to pixels of a half tone cell;

determining from said stored origin, length and direction data, addresses within said addressable memory of pixel intensity threshold data corresponding to particular pixels of said half tone cell array spanned by said line when said line is included in said graphic design,

sequentially addressing said addressable memory means with the determined addresses such that said addressable memory means reads out a sequence of said pixel intensity threshold data corresponding to the particular pixels;

successively comparing the stored line intensity data to the sequence of said pixel intensity threshold data read out of said addressable memory means;

producing a sequence of output bits, each successive output bit indicating a result of a successive comparison;

reading a first pixel data word out of said bit map memory, said first pixel data word comprising particular pixel data bits corresponding to said particular pixels; and

setting states of said particular pixel data bits of the read out first pixel data word in response to states of said output bits.

15. The method in acocrdance with claim 14 wherein the step of determining addresses comprises the substeps of:

generating a sequence of X address values indicating horizontal positions of said particular pixels within a half tone cell;

generating a sequence of Y address values indicating vertical positions of said particular pixels within said half tone cell; and

adding said X and Y address value sequences to produce a sequence of addresses for addressing said addressable memory means.

16. For a pixel processing system including a bit map memory storing pixel data bits, each pixel data bit corresponding to a separate pixel of a half tone cell array forming a graphic design and controlling appearance in said graphic design of said pixel data bit'"'"'s corresponding pixel, each half tone cell comprising a rectangular pixel array of adjustable horizontal and vertical dimensions, a half tone pixel processing method responsive to input origin data indicating an origin pixel within said half tone cell array of a line to be included in said graphic design, length data indicating a number of pixels of said half tone cell array spanned by said line, direction data indicating a direction of said line from said origin pixel, line intensity data indicating intensity of said line, and X and Y dimension data respectively indicating said horizontal and vertical dimensions, the half tone pixel processing method comprising the steps of:

storing said input origin, length, direction, intensity, and X and Y dimension data;

storing at various addresses of an addressable memory means pixel intensity threshold data corresponding to each pixel of a half tone cell;

determining from said stored origin, length, direction and X and Y dimension data a sequence of addresses within said addressable memory means of pixel intensity threshold data corresponding to particular pixels of said half tone cell array spanned by said line,

addressing said addressable memory means with said sequence of addresses such that said addressable memory means successively reads out a sequence of said pixel intensity threshold data corresponding to the particular pixels;

successively comparing the stored line intensity data to the sequence of pixel intensity threshold data read out of said addressable memory means and producing a sequence of output bits, each successive output bit indicating a result of a successive comparison; and

setting states of bits stored in said bit map memory corresponding to said particular pixels in response to states of said output bits.

17. The method in accordance with claim 16 wherein the step of determining addresses comprises:

generating a sequence of X address values indicating horizontal positions of said particular pixels within a half tone cell;

generating a sequence of Y address values indicating vertical positions of said particular pixels within said half tone cell; and

combining said X and Y address value sequences to produce said sequence of addresses addressing said addressable memory means.

18. For a pixel processing system including a bit map memory storing pixel data bits, each pixel data bit corresponding to a separate pixel of a half tone cell array forming a graphic design and controlling appearance in said graphic design of said pixel data bit'"'"'s corresponding pixel, each half tone cell comprising a rectangular pixel array of adjustable horizontal and vertical dimensions, a half tone pixel processing method responsive to input origin data indicating an origin pixel within said half tone cell array of a line to be included in said graphic design, length data indicating a number of pixels of said half tone cell array spanned by said line, direction data indicating a direction of said line from said origin pixel, line intensity data indicating intensity of said line, dimension data indicating horizontal and vertical dimensions of a half tone cell, and offset data indicating the adjustable offset of said half tone cell array, the half tone pixel processing method comprising the steps of:

storing said input origin, length, direction, intensity, X and Y dimension and offset data;

storing at various addresses in an addressable memory means pixel intensity threshold data corresponding to each pixel of a half tone cell;

determining from said stored origin, length, direction, X and Y dimension and offset data a sequence of addresses within said addressable memory means of pixel intensity threshold data corresponding to particular pixels of said half tone cell array spanned by said line,

sequentially addressing said addressable memory means with the sequence of addresses such that said addressable memory means successively reads out a sequence of said pixel intensity threshold data corresponding to the particular pixels;

successively comparing the stored line intensity data to the sequence of pixel intensity threshold data read out of said addressable memory means and producing a sequence of output bits, each successive output bit indicating a result of a successive comparison; and

setting states of bits stored in said bit map memory corresponding to said particular pixels in response to states of said output bits.