Logic cell array using CMOS EPROM cells having reduced chip surface area

• US 5,016,217 A
• Filed: 02/26/1990
• Issued: 05/14/1991
• Est. Priority Date: 05/17/1988
• Status: Expired due to Term

• Current Assignee: Analog Technologies Incorporated
• Original Assignee: ICT International CMOS Technology Incorporated
• Inventors: Brahmbhatt, Dhaval J.
• Primary Examiner(s): Hecker, Stuart N.
• Assistant Examiner(s): Sniezek, Andrew L.
• Application Number:
  US07/488,405
• Time in Patent Office: 442 Days
• Field of Search: 365/181, 365/184, 365/185, 365/189.08, 307/465, 307/469, 307/468, 307/23.5, 340/825.79, 340/825.83, 340/825.85, 340/825.86, 340/825.87, 340/825.90, 340/825.91, 340/825.93
• US Class Current: 365/185.1
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 16/0441 comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
• CPC Class Codes: G11C 16/045 Floating gate memory cells with both P and N channel memory transistors, usually sharing a common floating gate
• CPC Class Codes: H03K 3/356008 ensuring a predetermined initial state when the supply voltage has been applied; storing the actual state when the supply voltage fails digital storage cells each combining volatile and non-volatile storage properties G11C14/00
• CPC Class Codes: H03K 3/356104 using complementary field-effect transistors H03K3/35625 takes precedence

Abstract

An Electrically Programmable Read Only Memory (EPROM) memory cell includes a serially connected Complementary Metal Oxide Silicon (CMOS) transistor pair having common floating gates and common control gates. A third n-type floating gate field effect transistor is utilized for programming the memory cell. The floating gate and the control gate of the third transistor are connected to the common floating gates and the common control gates, respectively, of the Complementary Metal Oxide Silicon (CMOS) transistor pair. The memory cell is tri-statable by connecting the source of the p-channel transistor of the Complementary Metal Oxide Silicon (CMOS) pair to the common control gates.

Claims

1. A logic cell array comprising a plurality of configurable logic blocks arranged in rows and columns, each logic block including an ultraviolet light erasable EPROM memory cell, each EPROM memory cell having a serially connected CMOS transistor pair including a p-channel transistor having a source connected to a first terminal and an n-channel transistor having a source connected to a circuit ground potential, an output connected to a common terminal of said CMOS transistor pair, said CMOS transistor pair having a common floating gate and a common control gate, and means for selectively charging said common floating gate including an electrically programmable n-channel field effect transistor having a drain connected to a programming voltage terminal and a source connected to circuit ground potential, a floating gate connected to said common floating gate and a control gate connected to said common control gate, whereby said common floating gate receives electrons when positive voltages are applied to said programming voltage terminal and to said common control gate, said first terminal connected to said common control gate, each cell storing a "1" when said common control gate is at a positive voltage potential and said common floating gate has electrons stored thereon, each cell storing a "0" when said common control gate is at a positive voltage potential and said common floating gate has no electrons stored thereon, and each cell having a floating output when no positive voltage potential is applied to said common control gate.

2. An ultraviolet light erasable EPROM memory cell comprising a serially connected CMOS transistor pair including a p-channel transistor having a source connectable to a first terminal and an n-channel transistor having a source connectable to a circuit ground potential, and output connected to a common terminal of said CMOS transistor pair, said CMOS transistor pair having a common floating gate and a common control gate, and means for selectively charging said common floating gate including an electrically programmable n-channel field effect transistor having a drain connected to a programming voltage terminal and a source connected to circuit ground potential, a floating gate connected to said common floating gate and a control gate connected to said common control gate, whereby said common floating gate receives electrons when positive voltages are applied to said programming voltage terminal and to said common control gate, said first terminal connected to said common control gate, said cell storing a "1" when said common control gate is at a positive voltage potential and said common floating gate has electrons stored thereon, said cell storing a "0" when said common control gate is at a positive voltage potential and said common floating gate has no electrons stored thereon, and said cell having a floating output when no positive voltage potential is applied to said common control gate.