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Apparatus for generating a data stream

  • US 5,016,226 A
  • Filed: 11/09/1988
  • Issued: 05/14/1991
  • Est. Priority Date: 11/16/1987
  • Status: Expired due to Term
First Claim
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1. An apparatus for generating a data stream comprising:

  • clock means for providing a clock signal;

    address generating means coupled to said clock means for generating a sequence of addresses, said address generating means comprising address counter means, stepping in response to a frequency divided clock signal, for generation said sequence of addresses, and means for setting said address counter means to a start address;

    memory means responsive to said addresses, from which a plurality of words of data associated with each of said addresses are read in response to each of said addresses, said memory means comprises n+1 memory bank means, each memory bank means having an output from which data is read; and

    output means for sequentially outputting said plurality of words of data that is read from said memory means before the data associated with the next said address is read from said memory, said output means comprising a plurality of n+1 latches each of said latches connected to an associated one of said memory bank means for latching said plurality of words read from said memory means, and selection means coupled to said plurality of latch means for sequentially selecting each of said plurality of latch means in response to a selection signal and for sequentially outputting a word from the latch means selected based on said selection signal;

    control means coupled to said clock means, said control means performing control in synchronism with said clock signal such that said output means outputs only a portion of said plurality of words of data, said control means comprising frequency dividing means for dividing said clock signal by said switchable factor to produce a frequency divided clock signal, first counter means for generating said selection signal in response to said clock signal, said first counter means counting by a switchable modulus number, and second counter means stepping in response to said frequency divided clock signal, to produce a switching control output;

    said first counter means responsive to said switching control output for switching its modulus number between n and n+1 when said switching control output reaches a predetermined number; and

    said frequency dividing means responsive to said switching control output for switching its factor of frequency division between n and n+1 when said switching control output reaches said predetermined number.

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