Apparatus for generating a data stream

• US 5,016,226 A
• Filed: 11/09/1988
• Issued: 05/14/1991
• Est. Priority Date: 11/16/1987
• Status: Expired due to Term

• Current Assignee: Verigy Limited (Advantest Corporation)
• Original Assignee: HP Inc.
• Inventors: Kasuga, Nobuyuki, Hiwada, Kiyokasu
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/269,386
• Time in Patent Office: 916 Days
• Field of Search: 365/230.03, 365/230.04, 365/233, 365/189.05, 365/230.02, 365/189.02, 365/230.06, 365/236, 365/230.08, 365/230.09
• US Class Current: 365/233.17
• CPC Class Codes: G11C 8/04 using a sequential addressing device, e.g. shift register, counter

Abstract

In one embodiment of the invention, the selection of the number of the latches from which data is read can be changed dynamically during the generation of the data stream. The scanning of the latches can be stopped temporarily while the next set of data from the memory is stored in the latches, then resumed. For example, assume that n+1 number of banks are provided in the memory and that the selection of the number of the latches can be changed dynamically between n and n+1. Then, the possible length/period, N, of the data stream that can be generated would be:

N=i*n+j*(n+1)

where i and j are non-negative integers, and one of i or j is non-zero.

In another embodiment of the present invention, the memory has m+n banks, and the latch group has m+n latches. The number of the latches from which data is read during each scanning cycle can be selected from the range n, n+1, . . . , n+m-1, n+m. Consequently, any data stream having a length or period which is a multiple of any of n, n+1, . . . , n+m-1, n+m can be generated.

Claims

1. An apparatus for generating a data stream comprising:

clock means for providing a clock signal;

address generating means coupled to said clock means for generating a sequence of addresses, said address generating means comprising address counter means, stepping in response to a frequency divided clock signal, for generation said sequence of addresses, and means for setting said address counter means to a start address;

memory means responsive to said addresses, from which a plurality of words of data associated with each of said addresses are read in response to each of said addresses, said memory means comprises n+1 memory bank means, each memory bank means having an output from which data is read; and

output means for sequentially outputting said plurality of words of data that is read from said memory means before the data associated with the next said address is read from said memory, said output means comprising a plurality of n+1 latches each of said latches connected to an associated one of said memory bank means for latching said plurality of words read from said memory means, and selection means coupled to said plurality of latch means for sequentially selecting each of said plurality of latch means in response to a selection signal and for sequentially outputting a word from the latch means selected based on said selection signal;

control means coupled to said clock means, said control means performing control in synchronism with said clock signal such that said output means outputs only a portion of said plurality of words of data, said control means comprising frequency dividing means for dividing said clock signal by said switchable factor to produce a frequency divided clock signal, first counter means for generating said selection signal in response to said clock signal, said first counter means counting by a switchable modulus number, and second counter means stepping in response to said frequency divided clock signal, to produce a switching control output;

said first counter means responsive to said switching control output for switching its modulus number between n and n+1 when said switching control output reaches a predetermined number; and

said frequency dividing means responsive to said switching control output for switching its factor of frequency division between n and n+1 when said switching control output reaches said predetermined number.

2. The apparatus for generating a data stream as in claim 1, wherein said address generating means further comprises an address comparator means for comparing said addresses generated by said address counter means with a predetermined last address.

3. The apparatus for generating a data stream as in claim 2, wherein said apparatus stops its operation when said address comparator means detects that said address generated by said address counter means and said predetermined last address coincide.

4. The apparatus for generating a data stream as in claim 2, wherein said apparatus repeats its operation by setting said address counter means to said start address when said address comparator means detects that said address generated by said address counter means and said predetermined last address coincide.

5. The apparatus for generating a data stream as in claim 4, further comprising a third counter means for counting the number of repetitions of operation of said apparatus for generation of said data stream, for stopping said repetition when said number of repetitions reaches a predetermined repeat count.

6. An apparatus for generating a data stream comprising:

clock means for providing a clock signal;

address generating means coupled to said clock means for generating a sequence of addresses, said address generating means comprising address counter means, stepping in response to a frequency divided clock signal, for generating said sequence of addresses, and means for setting said address counter means to a start address;

memory means responsive to said addresses, from which a plurality of words of data associated with each of said addresses are read in response to each of said addresses, said memory means comprises n+m memory bank means, each memory bank means having an output from which data is read; and

output means for sequentially outputting said plurality of words of data that is read from said memory means before the data associated with the next said address is read from said memory, said output means comprising a plurality of n+m latches each of said latches connected to an associated one of said memory bank means for latching said plurality of words read from said memory means, and selection means coupled to said plurality of latch means for sequentially selecting each of said plurality of latch means in response to a selection signal and for sequentially outputting a word from the latch means selected based on said selection signal;

control means coupled to said clock means, said control means performing control in synchronism with said clock signal such that said output means outputs only a portion of said plurality of words of data, said control means comprising frequency dividing means for dividing said clock signal by a switchable factor selected from the range from n to n+m to produce said frequency divided clock signal, first counter means for generating said selection signal in response to said clock signal, said first counter means counting by a switchable modulus number selected from the range from n through n+m; and

second counter means stepping in response to said frequency divided clock signal, to produce a switching control output;

wherein said factor of frequency division of said frequency dividing means and said modulus number of said first counter means are set at the same number during generation of one data stream.

7. The apparatus for generating a data stream as in claim 6, wherein said address generating means further comprises an address comparator means for comparing said addresses generated by said address counter means with a predetermined last address.

8. The apparatus for generating a data stream as in claim 7, wherein said apparatus stops its operation when said address comparator means detects that said address generated by said address counter means and said predetermined last address coincide.

9. The apparatus for generating a data stream as in claim 7, wherein said apparatus repeats its operation by setting said address counter means to said start address when said address comparator means detects that said address generated by said address counter means and said predetermined last address coincide.

10. The apparatus for generating a data stream as in claim 9, further comprising a third counter means for counting the number of repetitions of operation of said apparatus for generation of said data stream, for stopping said repetition when said number of repetitions reaches a predetermined repeat count.