Buffer memory device for packet data and method of controlling the device

• US 5,016,248 A
• Filed: 10/25/1989
• Issued: 05/14/1991
• Est. Priority Date: 10/27/1988
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kudoh, Norimasa
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): HSU, ALPUS
• Application Number:
  US07/426,424
• Time in Patent Office: 566 Days
• Field of Search: 370/94.1, 370/60, 370/85.1, 370/85.6, 340/825.5, 340/825.51, 340/825.52, 364/200
• US Class Current: 370/413
• CPC Class Codes: H04J 3/0632 Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES] queuing arrangements in packet switching elements H04L49/90; synchronising systems for the synchronous transmission of a pulse code modulated video signal with one or more other pulse code modulated signals H04N7/56
• CPC Class Codes: H04L 49/103 using a shared central buffer; using a shared memory
• CPC Class Codes: H04L 49/3036 Shared queuing

Abstract

A buffer memory device and method for fixed-length packet data. The write and read addresses of a memory are controlled by respectively independent pointer queues and these pointer queues are arranged to be distributed to the address data queue of any of the packet queues. When data are concentrated on a specific packet queue, the address data of packet queues low in use frequently are distributed so that the writable area of the specific packet queue can be expanded.

Claims

1. A system for storing and reading data in a packet form, comprising:

a plurality of packet queue means for storing input packet data therein;

a plurality of first pointer queue means, each associated with a corresponding one of said packet queue means, for storing therein pointers indicative of addresses of writable areas in each of said packet queue means, respectively;

a plurality of second pointer queue means, each associated with a corresponding one of said packet queue means, for storing therein pointers indicative of addresses of readable areas in each of said packet queue means, respectively;

address control means for selecting an address of any one of said packet queue means to write packet data on the basis of the pointers stored in said first pointer queue means and for selecting an address of one of said packet queue means to read packet data on the basis of the pointers stored in said second pointer queue means; and

pointer control means, operable in response to a reading operation of a packet data from one of said packet queue means, for deleting a pointer, indicative of the address of that packet queue means where said packet data had been stored, from the one of the second pointer queue means where said pointer had been stored and for writing said pointer into one of said first pointer queue means.

2. The system as set forth in claim 1, wherein each of said plurality of packet queue means comprises a predetermined memory area in a single 2-port random access memory, respectively.

3. The system as set forth in claim 1, wherein said address control means select an address of any one of said packet queue means to which a packet data is to be written on the basis of a priority data attached to said packet data.

4. The system as set forth in claim 1, wherein said packet data is of a fixed length.

5. The system as set forth in claim 1, wherein said first and second pointer queue means each comprise, respectively, a memory.

6. The system as set forth in claim 1, wherein said pointer control means determines one of said first pointer queue means in which pointers are to be written in response to a number of pointers stored in said first pointer queue means.

7. A system for storing and reading data in a packet form, comprising:

a plurality of packet queue means for storing packet data therein;

a plurality of first pointer queue means, each associated with a corresponding one of said packet queue means, for storing therein pointers indicative of addresses of writable areas of said packet queue means, respectively;

a plurality of second pointer means, each associated with a corresponding one of said packet queue means, for storing therein pointers indicative of addresses of readable areas in each of said packet queue means, respectively;

packet distributing means for selecting any one of said first pointer queue means on the basis of a priority data attached to an input packet data and for selecting an address of any one of said packet queue means in accordance with a pointer stored in said selected first pointer queue means to thereby write said input packet data into the one of the packet queue means corresponding to the selected first pointer queue means; and

transmission packet deciding means for selecting any one of said second pointer queue means and for selecting an address of any one of said packet queue means in accordance with a pointer stored in said selected second pointer queue means to thereby read out packet data from one of said plurality of packet queue means, and, in response to a reading operation of packet data from the packet queue means, for deleting a pointer indicative of an address of the packet queue means where the read packet data had been stored from the second pointer queue means where said pointer had been stored and for writing the pointer into one of said first pointer queue means.

8. The system as set forth in claim 7, wherein each of said plurality of packet queue means comprises a predetermined memory area in a single 2-port random access memory, respectively.

9. The system as set forth in claim 7, wherein said packet data is of a fixed length.

10. The system as set forth in claim 7, wherein said first and second pointer queue means each comprise, respectively, a memory.

11. The system as set forth in claim 7, wherein said transmission packet deciding means determines one of said first pointer queue means in which a pointer is to be written in accordance with a number of pointers stored in said first pointer queue means.

12. A method of controlling a system for storing and reading data in a packet form, comprising the steps of:

selecting any one of a plurality of packet queue means in which a packet data is to be written on the basis of a priority data attached to said packet data;

selecting an address of said selected packet queue means on the basis of pointers stored in a plurality of first pointer queue means, each said first pointer queue means being associated with a corresponding one of said packet queue means, said pointers stored in said first pointer queue means being indicative of addresses of writable areas of said packet queue means;

selecting one of said plurality of packet queue means from which a packet data is to be read out;

selecting an address of said packet queue means on the basis of pointers stored in a plurality of second pointer queue means, each said second pointer queue means being associated with a corresponding one of said packet queue means, said pointers stored in said second pointer queue means being indicative of addresses of readable areas of said packet queue means; and

deleting, in response to a reading of a packet data from a packet queue means, a pointer indicative of an address of the packet queue means where the packet data had been stored from the second pointer queue means where said pointer had been stored and writing said pointer into any one of said first pointer queue means.

13. The method as set forth in claim 12, wherein said packet data is a of a fixed length.