Video display co-processor for use in a video game
First Claim
1. In a video game having a display system including a raster scan line video display unit, a supervisory digital computer for supervising the operation of the display system, a program memory that contains a computer program executed by the supervisory digital computer, an image memory that contains data for a plurality of images, a bit map memory for receiving and storing image data and for supplying such stored image data for display on the video display unit, and means for allowing a player of the video game to interact with the supervisory digital computer'"'"'s execution of the computer program to change the scene presented on the video display unit, the improvement which comprises:
- a Direct Memory Access ("DMA") co-processor operable under the control of signals from the supervisory digital computer for processing a raster scan video image, said DMA co-processor including;
a) Source Address Generation ("SAG") means for generating addresses of locations in the image memory from which image data is retrieved;
b) Data Pipe ("DP") means for receiving image data from locations in said image memory addressed by said SAG means, and for permitting pixel and image manipulation of such image data to adapt it for display on the video display unit prior to storing the manipulated data into the bit map memory;
c) Destination Address Generation ("DAG") means for generating addresses of locations in said bit map memory into which image data is stored after having been manipulated by said DP means;
d) Control Section ("CS") means for controlling the operation of said SAG means, said DP means and said DAG means in response to supervisory control signals received by said CS means from the supervisory digital computer;
e) a first data bus between said DP means and said image memory for transferring said image data from said image memory to said DP means prior to manipulation by said DP means, and;
f) a second data bus between said DP means and said bit map memory for transferring said image data from said DP means to said bit map memory after manipulation by said DP means.
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Accused Products
Abstract
Disclosed is a bit mapped raster display video game that includes a Direct Memory Access ("DMA") co-processor especially adapted for providing real-time animation of the image data. The DMA co-processor is adapted for combining multiple overlapping planes of image data occupying an addressable image area greater than that displayable on a video display during the time interval of a single video raster scan. As the image data is being combined, the DMA co-processor can also manipulate it to produce real-time animation. The DMA co-processor includes a Source Address Generation ("SAG") functional unit that generates the addresses of locations in an image memory from which image data is to be retrieved. Retrieved image data is manipulated within a Data Pipe ("DP") functional unit to provide images that move smoothly across the screen. Manipulated image data is stored into a bit map memory at address locations specified by a Destination Address Generation ("DAG") functional unit. A Control Section ("CS") functional unit receives image processing commands from a supervisory ditigal computer included in the video game to control the operation of the SAG, DP and DAG functional units.
81 Citations
20 Claims
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1. In a video game having a display system including a raster scan line video display unit, a supervisory digital computer for supervising the operation of the display system, a program memory that contains a computer program executed by the supervisory digital computer, an image memory that contains data for a plurality of images, a bit map memory for receiving and storing image data and for supplying such stored image data for display on the video display unit, and means for allowing a player of the video game to interact with the supervisory digital computer'"'"'s execution of the computer program to change the scene presented on the video display unit, the improvement which comprises:
a Direct Memory Access ("DMA") co-processor operable under the control of signals from the supervisory digital computer for processing a raster scan video image, said DMA co-processor including; a) Source Address Generation ("SAG") means for generating addresses of locations in the image memory from which image data is retrieved; b) Data Pipe ("DP") means for receiving image data from locations in said image memory addressed by said SAG means, and for permitting pixel and image manipulation of such image data to adapt it for display on the video display unit prior to storing the manipulated data into the bit map memory; c) Destination Address Generation ("DAG") means for generating addresses of locations in said bit map memory into which image data is stored after having been manipulated by said DP means; d) Control Section ("CS") means for controlling the operation of said SAG means, said DP means and said DAG means in response to supervisory control signals received by said CS means from the supervisory digital computer; e) a first data bus between said DP means and said image memory for transferring said image data from said image memory to said DP means prior to manipulation by said DP means, and; f) a second data bus between said DP means and said bit map memory for transferring said image data from said DP means to said bit map memory after manipulation by said DP means. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A video display system comprising
a raster scan line video display unit for displaying scenes; -
supervisory digital computer means for supervising the operation of the video display system; program memory means for storing a computer program executed by the supervisory digital computer; image memory means for storing data for a plurality of images; bit map memory means for receiving and storing image data and for supplying such stored image data for display on the video display unit, and; a Direct Memory Access ("DMA") co-processor operable under the control of signals from the supervisory digital computer for processing a raster scan video image, said DMA co-processor including; a) Source Address Generation ("SAG") means for generating addresses of locations in the image memory from which image data is retrieved; b) Data Pipe ("DP") means for receiving image data from locations in said image memory addressed by said SAG means, and for permitting pixel and image manipulation of such image data to adapt it for display on the video display unit prior to storing the manipulated data into the bit map memory; c) Destination Address Generation ("DAG") means for generating addresses of locations in said bit map memory into which image data is stored after having been manipulated by said DP means; d) Control Section ("CS") means for controlling the operation of said SAG means, said DP means and said DAG means in response to supervisory control signals received by said CS means from the supervisory digital computer; e) a first data bus between said DP means and said image memory for transferring said image data from said image memory to said DP means prior to manipulation by said DP means, and; f) a second data bus between said DP means and said bit map memory for transferring said image data from said DP means to said bit map memory after manipulation by said DP means. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A Direct Memory Access ("DMA") co-processor operable under the control of signals from a supervisory digital computer for use in a video display system for processing a raster scan video image, the video display system including a raster scan line video display for displaying scenes, a program memory which contains a computer program executed by the supervisory digital computer, an image memory which contains data for a plurality of images, and a bit map memory for receiving and storing image data in a format adapted for display on said video display and for supplying such stored image data to the video display unit, said DMA co-processor comprising:
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a) Source Address Generation ("SAG") means for generating addresses of locations in the image memory from which image data is retrieved; b) Data Pipe ("DP") means for receiving image data from locations in said image memory addressed by said SAG means, and for permitting pixel and image manipulation of such image data to adapt it for display on the video display unit prior to storing the manipulated data into the bit map memory; c) Destination Address Generation ("DAG") means for generating address of locations in said bit map memory into which image data is stored after having been manipulated by said DP means; d) Control Section ("CS") means for controlling the operation of said SAG means, said DP means and said DAG means in response to supervisory control signals received by said CS means from the supervisory digital computer; e) a first data bus between said DP means and said image memory for transferring said image data from said image memory to said DP means prior to manipulation by said DP means, and; f) a second data bus between said DP means and said bit map memory for transferring said image data from said DP means to said bit map memory after manipulation by said DP means. - View Dependent Claims (18, 19, 20)
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Specification