Vertical type MOS transistor and method of formation thereof

• US 5,017,504 A
• Filed: 04/21/1989
• Issued: 05/21/1991
• Est. Priority Date: 12/01/1986
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Sugahara, Kazukyuki, Kusunori, Shigeru, Ohsaki, Akihiko, Nishimura, Tadashi
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): Thomas, Tom
• Application Number:
  US07/341,596
• Time in Patent Office: 760 Days
• Field of Search: 437/919, 437/47, 437/60, 437/29, 437/40, 437/41, 437/228, 437/235, 437/249, 437/51, 437/52, 437/56, 437/89, 437/203, 437/233, 357/55, 357/23.6, 357/23.4, 156/643
• US Class Current: 438/269
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H10B 12/395 the transistor being vertical

Abstract

A vertical MOS transistor having its channel length determined by the thickness of an insulating layer provided over a semiconductor substrate, rather than by the depth of a trench in which the transistor is formed. As a result, the characteristics of the transistor as relatively unaffected by doping and heat-treatment steps which are performed during formation. Also, the transistor may be formed so as to occupy very little surface area, making it suitable for application in high-density DRAMs.

Claims

1. A method of forming a vertical type MOS transistor comprising the following steps:

(a) forming a first source-drain region (220 of a first conductivity type selectively in a major surface of a semiconductor substrate;

(b) forming an insulating layer (23) on a major surface of said semiconductor substrate;

(c) forming a trench (20) extending from the major surface of said insulating layer to at least the major surface of said first source-drain region, said trench having side walls and a bottom;

(d) forming a semiconductor layer (29) along said slide walls and said bottom of said trench and along a surface of said insulating layer at least near said trench;

(e) altering a portion of said semiconductor layer contacting the major surface of said substrate and located near a side wall of said insulating layer facing said trench such that said portion is monocrystalline;

(f) forming a gate insulator (26) on said semiconductor layer at least over said side walls and bottom of said trench;

(g) forming a gate electrode on said gate insulator at least in said trench; and

(h) forming a second source-drain region of said first conductivity type in said semiconductor layer over the major surface of said insulating layer and at least in said trench such that a channel length of said transistor is determined by a a thickness of said insulating layer, independent of a depth of said trench.

2. A method according to claim 1, wherein said step of forming said first source-drain region comprises the step of ion-implanting arsenic in said major surface of said semiconductor substrate.

3. A method according to claim 1, wherein said gate electrode comprises poly-silicon doped with phosphorus.

4. A method according to claim 1, wherein said second source-drain region is formed by ion-implantation of As.

5. A method according to claim 1, wherein said insulating layer comprises SiO₂.

6. A method according to claim 5, wherein said step of forming said insulating layer is accomplished by low pressure chemical vapor deposition (CVD).

7. A method according to claim 6, wherein the thickness of said SiO₂ is 1 μ

m.

8. A method according to claim 1, wherein said semiconductor layer comprises amorphous silicon.

9. A method according to claim 8, wherein said amorphous silicon layer is formed by depositing poly-silicon to form a poly-silicon layer and then implanting silicon in said poly-silicon layer.

10. A method according to claim 9, wherein said monocrystalline layer is formed by heat-treating of said amorphous silicon layer.