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Vertical type MOS transistor and method of formation thereof

  • US 5,017,504 A
  • Filed: 04/21/1989
  • Issued: 05/21/1991
  • Est. Priority Date: 12/01/1986
  • Status: Expired due to Fees
First Claim
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1. A method of forming a vertical type MOS transistor comprising the following steps:

  • (a) forming a first source-drain region (220 of a first conductivity type selectively in a major surface of a semiconductor substrate;

    (b) forming an insulating layer (23) on a major surface of said semiconductor substrate;

    (c) forming a trench (20) extending from the major surface of said insulating layer to at least the major surface of said first source-drain region, said trench having side walls and a bottom;

    (d) forming a semiconductor layer (29) along said slide walls and said bottom of said trench and along a surface of said insulating layer at least near said trench;

    (e) altering a portion of said semiconductor layer contacting the major surface of said substrate and located near a side wall of said insulating layer facing said trench such that said portion is monocrystalline;

    (f) forming a gate insulator (26) on said semiconductor layer at least over said side walls and bottom of said trench;

    (g) forming a gate electrode on said gate insulator at least in said trench; and

    (h) forming a second source-drain region of said first conductivity type in said semiconductor layer over the major surface of said insulating layer and at least in said trench such that a channel length of said transistor is determined by a a thickness of said insulating layer, independent of a depth of said trench.

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