Apparatus and method for combining analog detection signals to provide enhanced alarm integrity

• US 5,017,906 A
• Filed: 10/06/1989
• Issued: 05/21/1991
• Est. Priority Date: 10/06/1989
• Status: Expired due to Fees

• Current Assignee: Aritech BV
• Original Assignee: Aritech BV
• Inventors: Pantus, Math M. J.
• Primary Examiner(s): Crosland, Donnie L.
• Application Number:
  US07/418,130
• Time in Patent Office: 592 Days
• Field of Search: 340/517, 340/522, 340/506, 340/511, 340/661, 340/660, 340/870.01, 340/870.21, 340/537, 341/132, 341/126, 341/151, 341/158
• US Class Current: 340/517
• CPC Class Codes: G08B 29/183 Single detectors using dual technologies G08B13/1672, G08B13/2448, G08B13/2494 take precedence
• CPC Class Codes: G08B 29/22 Provisions facilitating manual calibration, e.g. input or output provisions for testing; Holding of intermittent values to permit measurement

Abstract

An apparatus and method for combining detection signals generated by intrusion detection systems to provide improved alarm integrity therefor. The apparatus and method have utility with mixed sensor technology and single sensor technology detection systems. In one embodiment, analog detection signals generated by system sensors are combined in an analog multiplier and the resulting decision signal is compared via a unipolar threshold comparator or a window comparator. In another embodiment, analog detection signals are amplitude limited prior to being combined in the analog multiplier. In a further embodiment, analog detection signals are subjected to average value processing such that the decision signal has a value equal to one-half of the sum of the sensor signals. In yet a further embodiment, analog dectection signals are amplitude limited prior to average value processing.

Claims

1. An apparatus for combining analog detection signals generated by single sensor technology and mixed sensor technology intrusion detection systems, comprising:

means for generating first and second analog detection signals;

means for combining said first and second analog detection signals to provide an alarm decision signal having an amplitude;

comparator means having at least one predetermined threshold for comparing said amplitude of said alarm decision signal to said at least one predetermined threshold, said comparator means being operative in response to said amplitude exceeding said at least one predetermined threshold to generate an output signal for triggering a system alarm;

signal limiting means coupled to said first and second analog detection signal generating means for limiting amplitudes of said first and second analog detection signals to a predetermined limit value; and

wherein said combining means provides said alarm decision signal having said amplitude equal to the amplitude of said first analog detection signal multiplied by the amplitude of said second analog detection signal.

2. The apparatus of claim 1 wherein said combining means comprises an analog multiplier.

3. The apparatus of claim 1 further comprising:

signal limiting means coupled to said first and second analog detection signal generating means for limiting amplitudes of said first and second analog detection signals to a predetermined limit value.

4. The apparatus of claim 1 wherein said comparator means comprises a first comparator having a high threshold and a second comparator having a low threshold;

and further comprising

OR means coupled to said first and second comparators for providing said output signal to trigger the system alarm whenever said amplitude of said alarm decision signal exceeds said high threshold and for providing said output signal to trigger the system alarm wherein said amplitude of said alarm decision signal exceeds said low threshold.

5. The apparatus of claim 1 wherein said combining means is a summing circuit for providing said alarm decision signal having said amplitude equal to the amplitude of said first analog detection signal added to the amplitude of said second analog detection signal, the sum thereof divided by two.

6. The apparatus of claim 5 wherein said summing circuit consists of first and second resistors coupled respectively to said first and second analog detection signal generating means and one another to provide said alarm decision signal having said amplitude equal to the amplitude of said first analog detection signal added to the amplitude of said second analog detection signal, the sum thereof divided by two.

7. The apparatus of claim 6 wherein said first and second resistors have equal values.

8. The apparatus of claim 6 further comprising:

signal limiting means coupled to said first and second analog detection signal generating means for limiting amplitudes of said first and second analog detection signals to a predetermined limit value.

9. The apparatus of claim 6 wherein said comparator means comprises a first comparator having a high threshold and a second comparator having a low threshold;

and further comprising

OR means coupled to said first and second comparators for providing said output signal to trigger the system alarm whenever said amplitude of said alarm decision signal exceeds said high threshold and for providing said output signal to trigger the system alarm wherein said amplitude of said alarm decision signal exceeds said low threshold.