Sample-and-hold unit with high sampling frequency

• US 5,017,924 A
• Filed: 04/26/1990
• Issued: 05/21/1991
• Est. Priority Date: 05/03/1989
• Status: Expired due to Fees

• Current Assignee: Thomson Composants Microondes
• Original Assignee: Thomson Composants Microondes
• Inventors: Ruggeri, Stephane, Guiberteau, Christian, Le Paih, Michele
• Primary Examiner(s): Sotomayor, John B.
• Application Number:
  US07/514,888
• Time in Patent Office: 390 Days
• Field of Search: 342/195, 342/175, 307/352, 307/353, 328/151
• US Class Current: 342/195
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence

Abstract

Disclosed is a sample-and-hold unit more especially designed to work at microwave frequencies (>1 GHz). In order to increase the sampling frequency, the disclosed circuit has at least two identical parallel channels. Each channel has a first follower switch (9) a capacitor (11) and a second holding switch (15). The channels are controlled by a single clock, the complementary or phase-shifted signals (H, H) of which address the samples sequentially towards the output (8). The disclosed device can be applied to the processing of analog signals.

Claims

1. A sample and hold unit comprising:

an input for receiving an input signal;

at least two parallel circuits, each receiving said input signal and each parallel circuit comprising;

a first follower switch to load a sample of said input signal into a capacitor when said first switch is closed;

a second holder switch to transfer the loaded sample to an output when said second switch is closed;

a sampling clock signal for controlling said first and second switches of a first parallel circuit; and

at least one phase-shifted sampling clock signal for controlling said first and second switches of a respective at least one second parallel circuit;

wherein each of said parallel circuits sequentially transmits to said output the sample loaded in the capacitor of said respective parallel channel when said second switch of said respective parallel channel is closed.

2. A sample-and-hold unit according to claim 1 comprising only two parallel circuits, wherein the single sampling clock gives the complementary clock signals H and H, one of which, namely H, is applied to the following switch of a first circuit and to the holding switch of a second circuit, and the complement of which, namely H, is applied to the holding switch of a first circuit and to the following switch of a second circuit.

3. A sample-and-hold unit according to claim 2, wherein amplifiers are interposed in each circuit behind the switches in order to prevent transfers of charges between circuits.

4. A sample-and-hold unit according to claim 1, comprising a plurality of identical, parallel circuits, the second switches of which are brought together in a single multiplexer which makes a sequential transmission, to the output, of the sample loaded in the capacitor of a given circuitry.

5. A sample-and-hold unit according to claim 4, wherein a single sampling clock controls the first follower switches by means of phase-shifted signals (H, H+Φ

, H+2Φ

. . . , H+(n-1)Φ

), and the multiplexer by means of a signal, the frequency of which is a multiple (nf_E) of the sampling frequency (f_E) on the parallel circuits, the coefficient of multiplication being equal to the number of parallel circuits.

6. A sample-and-hold unit according to claim 4, wherein there is a partial overlapping between the periods of following the input signal of two adjacent circuits, with one circuit beginning to load its capacitor before the preceding circuit has finished loading its own.

7. A sample-and-hold unit according to any one of claims 1 or 2, wherein the switches are transistors.