Dual EPROM cells on trench walls with virtual ground buried bit lines

• US 5,017,977 A
• Filed: 01/19/1990
• Issued: 05/21/1991
• Est. Priority Date: 03/26/1985
• Status: Expired due to Fees

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Richardson, William F.
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US07/471,019
• Time in Patent Office: 487 Days
• Field of Search: 357/23.5, 357/23.4, 357/23.6, 357/23.3, 357/55, 365/185
• US Class Current: 257/316
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

One embodiment of the present invention provides an EPROM array having floating gate field effect transistors formed on the sidewalls of trenches formed in a semiconducting substrate. Simultaneous with the fabrication of these trench wall transistors, column lines are formed between the trenches to the top surface in the bottom of the trenches which extend from one end to the other of the memory array.

Claims

1. An eraseable programmable read-only memory comprising:

(a) a substrate containing a plurality of elongated, parallel trenches;

(b) a plurality of first source/drain regions formed in said substrate near the bottom of said trenches, all of said first source/drain regions near the bottom of a single one of said trenches being connected together but isolated from all of said first source/drain regions near the bottom of others of said trenches;

(c) a plurality of second source/drain regions formed on the surface of said substrate near the mouth of said trenches;

(d) a plurality of third source/drain regions formed on the surface of said substrate near the mouth of said trenches on the opposite side of said trenches from said plurality of second source/drain regions and directly opposite said second source/drain regions;

(e) a plurality of first channel regions in said substrate extending substantially vertically between said first and said second source/drain regions;

(f) a plurality of second channel regions in said substrate extending substantially vertically between said first and said third source/drain regions;

(g) a plurality of first floating gates disposed on a sidewall of said trenches adjacent to and insulated from said first channel regions;

(h) a plurality of second floating gates disposed on a sidewall of said trenches adjacent to and insulated from said second channel regions;

(i) a plurality of first control gates extending into said trenches adjacent to, insulated from and capacitively coupled to respective corresponding ones of said plurality of first floating gates; and

(j) a plurality of second control gates extending into said trenches adjacent to, insulated from, and capacitively coupled to respective corresponding ones of said plurality of second floating gates.

2. An array of floating gate transistors arranged in rows and columns, comprising:

a substrate containing a plurality of elongated, parallel trenches;

a plurality of first source/drain regions formed in said substrate near the bottom of said trenches, all of said first source/drain regions near the bottom of a single one of said trenches being connected together but isolated from all of said first source/drain regions near the bottom of others of said trenches;

a plurality of second source/drain regions formed on the surface of said substrate near the mouth of said trenches;

a plurality of third source/drain regions formed on the surface of said substrate near the mouth of said trenches on the opposite side of said trenches from said plurality of second source/drain regions and directly opposite said second source/drain regions;

a plurality of first channel regions in said substrate extending substantially vertically between said first and said second source/drain regions;

a plurality of second channel regions in said substrate extending substantially vertically between said first and said third source/drain regions;

a plurality of first floating gates disposed on a sidewall of said trenches adjacent to and insulated from said first channel regions;

a plurality of second floating gates disposed on a sidewall of said trenches adjacent to and insulated from said second channel regions;

a plurality of first control gates extending into said trenches adjacent to, insulated from and capacitively coupled to respective corresponding ones of said plurality of first floating gates; and

a plurality of second control gates extending into said trenches adjacent to, insulated from, and capacitively coupled to respective corresponding ones of said plurality of second floating gates.

3. An array of floating gate field effect transistors according to claim 2 wherein each of said first floating gates overlaps respective first and second source/drain regions and each of said second floating gates overlaps respective first and third source/drain regions.

4. An array of floating gate field effect transistors as in claim 2, wherein said substrate comprises crystalline silicon.

5. An array of floating gate field effect transistors as in claim 2 wherein each row of floating gate field effect transistors includes a respective plurality of first and second control gates, said respective plurality of first and second control gates for each row of floating gate field effect transistors being electrically connected.

6. An array of floating gate field effect transistors according to claim 2, wherein each row of floating gate field effect transistors includes a respective plurality of first and second control gates, said respective plurality of first and second control gates for each row of floating gate field effect transistors being provided by a single control gate extending into said trenches.