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Timing circuit for memory employing reset function

  • US 5,018,111 A
  • Filed: 12/27/1988
  • Issued: 05/21/1991
  • Est. Priority Date: 12/27/1988
  • Status: Expired due to Term
First Claim
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1. A timing circuit for providing a plurality of control signals to control accessing of data from or to a memory comprising:

  • a first circuit means for receiving a first input signal and for providing a first output response to said first input signal;

    a plurality of second circuit means each representing scaled versions of actual memory components and each for providing a timed delay earlier in time to the actual delay in memory, said timed delay representing the time required for performing a function needed to access said memory, said plurality of second circuit means being coupled in series, the first one of said plurality of second circuit means being coupled to receive said first output signal, the last one of said plurality of second circuit means being coupled to provide a second input signal to said first circuit means;

    said first circuit means providing a second output signal in response to said second input signal;

    said first output signal and said second output signal each being delayed by at least one of said plurality of second circuit means, and after being so delayed, each being coupled to provide at least one of said control signals for a single memory cycle.

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