High resolution sample clock generator with deglitcher

• US 5,018,169 A
• Filed: 06/21/1989
• Issued: 05/21/1991
• Est. Priority Date: 06/21/1989
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Guinea, Jesus, Wong, Hee
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US07/369,474
• Time in Patent Office: 699 Days
• Field of Search: 375/118, 375/120, 375/119, 375/81, 375/82, 331/18, 331/49, 329/122, 329/307, 329/346, 328/63, 328/155, 328/133
• US Class Current: 375/373
• CPC Class Codes: H03L 7/0996 Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/0337 Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals

Abstract

A digital controlled clock provides ultra fine resolution for a sampling clock signal for recovering data from a received signal, the phase jump of the sampling clock signal being determined the number of stages in a multiphase clock generator that generates a number of equally-spaced phase clock outputs based on a reference clock signal. Phase selection is performed through a very low overhead phase commutator in response to phase advance/retard inputs. A clock deglitcher matched to the stages of the ring oscillator eliminates spikes generated when the phase commutator switches.

Claims

1. A digital controlled clock, comprising:

(a) means for generating a plurality of phase clock signals having an equally-spaced phase relationship;

(b) commutator means for selecting one of the plurality of phase clock signals; and

(c) deglitcher circuitry for removing spikes from the selected phase clock signal, the deglitcher circuitry comprising

(i) a first delay stage for delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output signal;

(ii) a second delay stage for delaying the first delay stage output signal by a second preselected amount to provide a second delay stage output signal; and

(iii) a NAND gate which receives the first and second delay stage output signals as inputs and provides a sample clock signal as an output signal.

2. A digital controlled clock for generating a sample clocks signal for use in recovering data from a received signal, the digital controlled clock comprising:

(a) a multi-phase clock generator comprising

(i) a crystal oscillator that provides a reference clock signal having a preselected frequency;

(ii) a multi-stage ring oscillator that provides a plurality of phase clock signals having the preselected frequency and an equally-spaced phase relationship; and

(iii) locking means connected to receive the reference clock signal and one of the phase clock signals for locking the frequency of the phase clock signals to the preselected frequency;

(b) a phase commutator for selecting one of the phase clock signals, the phase commutator comprising

(i) a multiplexor that receives the plurality of phase clock signal as input signals and provides the selected phase clock signal as an output signal based on a select input signal to the multiplexor; and

(c) clock deglitcher circuitry for removing spikes from the selected phase clock signal to provide the sample clock signal, the clock deglitcher circuitry comprising

(i) a first delay stage for delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output signal;

(ii) a second delay stage for delaying the first delay stage output signal by a second preselected amount to provide a second delay stage output; and

(iii) a NAND gate which receives the first and second delay stage output signals as input signals and provides the sample clock signal as an output signal.

3. A digital controlled clock for generating a sample clock signal for use in recovering data from a received signal, the digital controlled clock comprising:

(a) a multi-phase clock generator comprising

(i) a crystal oscillator that provides a reference clock signal having a preselected frequency;

(ii) a multi-stage ring oscillator that provides a plurality of phase clock signals having the preselected frequency and an equally-spaced phase relationship; and

(iii) an analog phase locked loop connected to receive the reference clock signal and one of the phase clock signals for locking the frequency of the phase clock signals to the preselected frequency;

(b) a phase commutator for selecting one of the phase clock signals comprising

(i) a multiplexor that receives the plurality of phase clock signals as inputs and provides the selected phase clock signal as an output based on a select input signal to the multiplexor; and

(ii) means responsive to a phase advance/retard input signal for generating the select input signal; and

(c) clock diglitcher circuitry for removing spikes from the selected phase clock signal to provide the sample clock signal wherein the clock deglitcher circuitry comprises;

a first delay stage for delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output;

a second delay stage for delaying the first delay stage output by a second preselected amount to provide a second delay stage output; and

a NAND gate which receives the first and second delay stage outputs as inputs and provides the sample clock as an output.

4. A digital controlled clock as in claim 3 wherein the multi-stage ring oscillator comprises a plurality of series-connected inverter elements and wherein the first delay stage comprises a pair of series-connected inverter elements and the second delay stage comprises two pair of series-connected inverter elements, each of the inverter elements of the first and second delay stages being matched to the inverter elements of the multi-stage ring oscillator.

5. A digital controlled clock as in claim 3 and further comprising:

(a) a third delay stage for delaying the sample clock signal by the second preselected amount to provide a third delay stage output; and

(b) a second NAND gate which receives the sample clock signal and the third delay stage output as inputs and provides a sample clock output having a preselected duty cycle.

6. A digital controlled clock as in claim 5 wherein the third delay stage comprises two pair of series-connected inverter elements that are matched to the inverter elements of the multi-stage ring oscillator such that the sample clock output has a 50/50 duty cycle.

7. A digital controlled clock for generating a sample clock signal for use in recovering data from a received signal, the digital controlled clock comprising:

(a) multiphase-clock generator comprising

(i) a crystal oscillator that provides a reference clock signal having a preselected frequency;

(ii) a voltage controlled oscillator (VCO) comprising a plurality of series-connected inverters arranged in a ring configuration, the output of each inverter providing one of a plurality of phase clock signals having the preselected frequency and an equally-spaced phased relationship; and

(iii) an analog phase locked loop connected to receive the reference clock signal and one of the phase clock signals for generating a control voltage signal for the VCO such that the frequency of the phase clock signals is locked to the preselected frequency;

(b) phase commutator for selecting one of the phase clock signals, the phase commutator comprising

(i) multiplexor means for selecting one of the plurality of phase clock signals in response to a select signal;

(ii) a state machine responsive to an input signal for providing the select signal; and

(iii) storage means for storing the previous state machine input signal and responsive to an advance/retard input code for providing an updated state machine input signal; and

(c) deglitcher means for removing spikes from the selected phase clock signal to provide the sample clock signal, the deglitcher means comprising

(i) a first delay stage for delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output signal;

(ii) a second delay stage for delaying the first delay stage output signal by a second preselected amount to provide a second delay stage output signal; and

(iii) a NAND gate which receives the first and second delay stage output signals as input signals and provides the sample clock signal as an output signal.

11. A digital controlled clock as in claim 7 wherein the advance/retard input code to the storage means comprises a two-bit code wherein a first bit enables the phase commutator to make phase jumps among the plurality of clock signals and second bit determines the direction of the phase jump.

8. A digital controlled clock for generating a sample clock signal for use in recovering data from a received signal, the digital controlled clock comprising:

(a) a multi-phase clock generator comprising

(i) a crystal oscillator that provides a reference clock signal having a preselected frequency;

(ii) a voltage controlled oscillator (VCO) comprising a plurality of series-connected inverters arranged in a ring configuration, the output of each inverter providing one of a plurality of phase clock signals the preselected frequency and an equally-spaced phase relationship; and

(iii) an analog phase locked loop connected to receive the reference clock signal and one of the phase clock signals for generating a control voltage signal for the VCO such that the frequency of the phase clock signals is locked to the preselected frequency;

(b) a phase commutator for selecting one of the phase clock signals comprising

(i) multiplexor means for selecting one of the plurality of phase clock signals in response to a select signal;

(ii) a state machine responsive to an input signal for providing the select signal; and

(iii) storage means for storing the previous sate machine input signal and responsive to an advance/retard input code for providing an updated state machine input signal; and

(c) deglitcher means for removing spikes from the selected phase clock signal to provide the sample clock signal and wherein the deglitcher means comprises;

a first delay stage comprising two series-connected inverters for delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output;

a second delay stage comprising four series-connected inverters for delaying the first delay stage output by a second preselected amount to provide a second delay stage output; and

a NAND gate which receives the first and second delay stage outputs as inputs and provides the sample clock signal.

9. A digital controlled clock as in claim 8 wherein each of the inverters comprising the first and second delay stages is matched to the inverters of the VCO.

10. A digital controlled clock as in claim 9 and further comprising:

(a) a third delay stage comprising four inverters, each of which is matched to the inverters comprising the VCO, for delaying the sample clock signal by the second preselected amount to provide a third delay stage output; and

(b) a second NAND gate which receives the sample clock signal and the third delay stage output and provides a sample clock output having a 50/50 duty cycle.

12. A method of generating a sample clock signal, the method comprising:

(a) generating a plurality of phase clock signals having an equally-spaced phase relationship;

(b) selecting one of the plurality of phase clock signals;

(c) delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output signal;

(d) delaying the first delay stage output signal by a second preselected amount to provide a second delay stage output signal; and

(e) logically NANDing the first and second delay stage output signals to generate the sample clock signal

whereby voltage spikes are removed from the sample clock signal.

13. A method of generating a sample clock signal for use in recovering data from a received signal, the method comprising:

(a) providing a reference clock signal having a preselected frequency;

(b) providing a plurality of phase clock signals having an equally-spaced phase relationship;

(c) locking the frequency of the phase clock signals to the preselected frequency;

(d) selecting one of the phase clock signals;

(e) removing spikes from the selected phase clock signal to provide the sample clock signal,

wherein the step of removing spikes from the selected phase clock signal comprises;

delaying the selected phase clock signal by a first preselected amount to provide a first delay stage output signal;

delaying the first stage delay output signal by a second preselected amount to provide a second delay stage output; and

providing the first and second delay stage outputs as inputs to a NAND gate which provides the sample clock signal as an output.

14. A method as in claim 13 and further comprising:

(a) delaying the sample clock signal by the second preselected amount to provide a third delay stage output; and

(b) providing the sample clock signal and the third delay stage output as inputs to a second NAND gate which provides a sample clock output having a preselected duty cycle.

15. A method as in claim 14 wherein the sample clock output has a 50/50 duty cycle.