Coherently interruptible frequency hopped chirp generator

• US 5,019,825 A
• Filed: 11/24/1989
• Issued: 05/28/1991
• Est. Priority Date: 11/24/1989
• Status: Expired due to Fees

• Current Assignee: United States Of America As Represented By The Secretary Of The Army (Government of the United States of America)
• Original Assignee: The United States Of America As Represented By The Secretary Of The Army
• Inventors: McCorkle, John
• Primary Examiner(s): Sotomayor, John B.
• Application Number:
  US07/440,944
• Time in Patent Office: 550 Days
• Field of Search: 342/201, 342/202, 342/204, 307/106
• US Class Current: 342/201
• CPC Class Codes: G01S 13/28 with time compression of received pulses

Abstract

A coherently interruptible frequency hopped chirp waveform generator has aignal generating synthesizer and a chirp generator with digitally stored chirp samples in which both are phase locked to a reference clock and responsive to a timing and control circuit. The digitally stored chirp signal sample is D/A converted and mixed with a fixed frequency signal generated by the synthesizer forming translated chirp signals. The translated chirp signals are output, being controlled by a timing and control circuit so that a plurality of coherently interruptible and frequency selectable chirp sub-pulses are formed.

Claims

1. A circuit comprising:

synthesizing means for generating fixed frequency signals;

chirp generating means for generating chirp signals from a digital memory storing a chirp signal sample; and

chirp sub-pulse generating means responsive to the fixed frequency signals and the chirp signals for generating a plurality of coherently interruptible and frequency selectable chirp sub-pulses.

2. The circuit of claim 1 wherein said chirp sub-pulse generating means comprises:

a reference clock connected to said synthesizing means and said chirp generating means so that the fixed frequency signals generated by said synthesizing means and the chirp signals generated by said chirp generating means are phase locked to said reference clock.

3. The circuit of claim 2 wherein said chirp sub-pulse generating means further comprises:

mixing means for mixing the chirp signals with the fixed frequency signals forming frequency translated chirp signals;

timing and control means for controlling the frequency of the fixed frequency signals generated by said synthesizing means and for controlling said chirp generating means to generate the chirp signals at selectable increments of time so that the fixed frequency signals and the chirp signals are phase matched at selectable increments of time;

output means connected to said mixing means and responsive to said timing and control means for outputting the translated chirp signals in the form of a plurality of coherently interruptible and frequency selectable chirp sub-pulses.

4. The circuit of claim 3 wherein said mixing means comprises:

a plurality of power splitters connected to said synthesizer means and said chirp generating means;

a plurality of mixers connected to said plurality of power splitters;

a plurality of hybrid couplers connected to said mixers.

5. The circuit of claim 3 wherein said mixing means is a single sideband mixing means.

6. The circuit of claim 1 wherein said chirp generating means comprises:

a digital memory for storing a chirp signal sample;

at least one digital-to-analog converter connected to said digital memory;

a counter responsive to said chirp sub-pulse generating means for initiating said digital memory to output the chirp signal sample.

7. The circuit of claim 1 wherein the combination of said synthesizing means, said chirp generating means, and said chirp sub-pulse generating means outputs the plurality of coherently interruptible and frequency selectable chirp sub-pulses according to the following criterion:

space="preserve" listing-type="equation">s(t)=A.sub.j sin (ω

.sub.j (t-B.sub.j)+ψ

(t-B.sub.j).sup.2);

T.sub.j <

t<

T.sub.j+1

wherein;

s(t) is the outputted translated chirp signal,

j counts the sub-pulses,

A_j is the amplitude of the j^th subpulse,

t is time in seconds, ψ

is the ramp rate in radians per second per second,

T_inc =π

/ψ

is the time between zero crossings,

i_j is a set of integers,

T_j is equal to i_j ·

T_inc,

n_j is a set of integers,

B_j is equal to n_j ·

T_inc,

m_j is a set of integers,

ω

_j =2π

m_j /Tinc is the radian frequency of said synthesizing means 2 on the j^th sub-pulse.

8. The circuit of claim 1 wherein said sub-pulse generating means interrupts the plurality of chirp sub-pulses at zero crossings.

9. A circuit comprising:

synthesizing means for generating fixed frequency signals;

chirp generating means for generating chirp signals from a digital memory storing a chirp signal sample;

mixing means for mixing the chirp signals with the fixed frequency signals forming translated chirp signals;

output means connected to said mixing means;

timing and control means for controlling the frequency of the fixed frequency signals generated by said synthesizing means, and for controlling said chirp generating means to generate the chirp signals stored in the digital memory at selectable increments of time and at selectable points in the memory so that the fixed frequency signals and the chirp signals are phase matched at selectable increments of time, and for controlling said output means to output the translated chirp signals in the form of a plurality of coherently interruptible and frequency selectable chirp sub-pulses.

10. The circuit of claim 9 wherein the combination of said synthesizing means, said chirp generating means, said mixing means, said output means, and said timing and control means outputs the plurality of coherently interruptible and frequency selectable chirp sub-pulses according to the following criterion:

space="preserve" listing-type="equation">s(t)=A.sub.j sin (ω

.sub.j (t-B.sub.j)+ψ

(t-B.sub.j).sup.2);

T.sub.j <

t<

T.sub.j+1

wherein;

s(t) is the outputted translated chirp signal,

j counts the sub-pulses,

A_j is the amplitude of the j^th subpulse,

t is time in seconds,

ψ

is the ramp rate in radians per second per second,

T_inc =π

/ψ

is the time between zero crossings,

i_j is a set of integers,

T_j is equal to i_j ·

T_inc,

n_j is a set of integers,

B_j is equal to n_j ·

T_inc,

m_j is a set of integers,

ω

_j =2π

m_j /Tinc is the radian frequency of said synthesizing means 2 on the j^th sub-pulse.

12. The circuit of claim 9 wherein the combination of said reference clock, means, said synthesizing means, said chirp generating means, said mixing means, said timing and control means, and said output means, outputs the plurality of coherently interruptible and frequency selectable chirp sub-pulses according to the following criterion:

space="preserve" listing-type="equation">s(t)=A.sub.j sin (ω

.sub.j (t-B.sub.j)+ψ

(t-B.sub.j).sup.2);

T.sub.j <

t<

T.sub.j+1

wherein;

s(t) is the outputted translated chirp signal,

j counts the sub-pulses,

A_j is the amplitude of the j^th subpulse,

t is time in seconds,

ψ

is the ramp rate in radians per second per second,

T_inc =π

/ψ

is the time between zero crossings,

i_j is a set of integers,

T_j is equal to i_j ·

T_inc,

n_j is a set of integers,

B_j is equal to n_j ·

T_inc,

m_j is a set of integers,

ω

_j =2π

m_j /Tinc is the radian frequency of said synthesizing means 2 on the j^th sub-pulse.

11. A coherently interruptible frequency hopped chirp waveform generator comprising:

a reference clock;

synthesizing means responsive to said reference clock for generating quadrature fixed frequency signals;

chirp generating means locked onto said reference clock for generating quadrature chirp signals from a digital memory storing a quadrature chirp signal sample;

mixing means for mixing the quadrature fixed frequency signals with the quadrature chirp signals forming translated quadrature chirp signals;

timing and control means phase locked onto said reference clock for adjustably controlling the frequency of the quadrature fixed frequency signals generated by said synthesizing means and for controlling said chirp generating means to selectively generate the quadrature chirp signals from various read points in the digital memory at selectable increments of time so that the quadrature fixed frequency signals and the quadrature chirp signals are phase matched and frequency selectable; and

output means connected to said mixing means and responsive to said timing and control means for outputting the mixed quadrature chirp signals in the form of a plurality of coherently interruptible and frequency selectable chirp sub-pulses.