Input protective apparatus of semiconductor device

• US 5,019,883 A
• Filed: 11/30/1989
• Issued: 05/28/1991
• Est. Priority Date: 01/28/1987
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Mori, Shigeru, Murakami, Shuji, Yamada, Michihiro, Miyatake, Hideshi
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): NGO, NGAN V
• Application Number:
  US07/443,864
• Time in Patent Office: 544 Days
• Field of Search: 357/23.13, 357/51, 357/59 F, 357/59 G, 357/59 I, 357/41
• US Class Current: 257/360
• CPC Class Codes: H01L 23/647 Resistive arrangements H01L23/66, H01L23/62 take precedence
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance
• CPC Class Codes: H02H 7/20 for electronic equipment for converters H02H7/10; for electric measuring instruments G01R1/36; for dc voltage or current semiconductor regulators G05F1/569; for amplifiers H03F1/52; for electronic switching circuits H03K17/08

Abstract

An input protective apparatus for a semiconductor device (Q3) comprises an MOS transistor (Q4) having a thick gate insulating film formed therein. The MOS transistor (Q4) has one active layer connected to an input terminal (11) through a second resistor element (R2) and connected to a semiconductor device (Q3) to be protected through a first resistor element (R1), and an other active layer connected to a ground terminal. The input protective apparatus is adapted such that a resistance value R₁ of a first resistor element (R1) and a resistance value R₂ of the second resistor element (R2) satisfy the relation R₁ >R₂, and the on-resistance R₃ of the MOS transistor (Q4) and the resistance value R₂ satisfy the relation R₃ <<R₂.

Claims

1. An input protective apparatus for a semiconductor device (Q3), comprising an MOS transistor (Q4) having one active layer connected through a first resistor element (R1) to an input node of said device (Q3) and another active layer connected to a ground terminal of said device, a gate of said MOS transistor formed with a thick oxide insulating film,

which further comprises an external terminal (11) receiving an input signal to be applied to the input node of said semiconductor device (Q3) and a second resistor element (R2) connected between said external terminal (110 and one of the active layers of said MOS transistor (Q4),

a resistance value R₁ of said first resistor element (R1) and a resistance value R₂ of said second resistor element (R2) having the relation R₁ >

R₂, and said MOS type transistor being formed such that an on-resistance R₃ thereof satisfies a relation R₃ <

<

R₂.

2. An input protective apparatus as recited in claim 1 wherein said second resistor element is formed of a double layer structure, including polysilicon and a refractory metal.

3. An input protective device as recited in claim 1, wherein the resistance value of said second resistor element is several tens ohm.

4. An input protective device as recited in claim 3 wherein the resistance value of said second resistor element is in the range of 30 to 50 ohms.

5. An input protective device as recited in claim 3 wherein the resistance value of said first resistor element is several 100 ohms.

6. An input protective device as recited in claim 5 wherein said on-resistance R₃ is several ohms.

7. An input protective device as recited in claim 3 wherein said on-resistance R₃ is several ohms.

8. An input protective apparatus for a semiconductor device as recited in claim 1, wherein

said MOS type transistor (Q⁴) has a gate oxide film formed by selectively oxidizing a region between active layers (111, 112) serving as a source and a drain each formed on a semiconductor substrate, so that a length of said active layers along said gate oxide film is more than 100 μ

m, spacing between said active layers is less than 2 μ

m, and the on-resistance is several Ω

, wherein the resistance value R₁ of said first resistor element (R1) is several hundreds Ω and

the resistance value R₂ of said second resistor element (R2) is about 30 to 50 Ω

.

9. An input protective apparatus for a semiconductor device as recited in claim 1, wherein

a total area of one of said active layers of said MOS type transistor (Q⁴) is more than 2500 μ

m², an area of a contact region between one of said active layers and an interconnection layer is more than 300 μ

m², and spacing between edges of said contact region and said active layer is more than 5 μ

m.

10. An input protective apparatus for a semiconductor device as recited in claim 1, wherein

said second resistor element (R2) is formed of a stripe-like polysilicon layer having a width of more than 50 μ

m, an area of a contact region between a first interconnection layer and said second resistor element (R2) is more than 250 μ

m², said first interconnection layer connecting said second resistor element (R2) to said input terminal (11), and an area of a contact region between a second interconnection layer and said second resistor element is more than 250 μ

m², said second interconnection layer connecting said second resistor element to one of the active layers of said MOS type transistor (Q3).

11. An input protective apparatus for a semiconductor device as recited in claim 1, wherein

said second resistor element (R2) is formed of a stripe-like film having a two-layer structure comprising polysilicon and a refractory metal and having a width of more than 25 μ

m, and an area of a contact region between a first interconnection layer and said second resistor element (R2) is more than 250 μ

m², said first interconnection layer connecting said second resistor element (R2) to said input terminal (101), and an area of a contact region between a second interconnection layer and said second resistor element is more than 250 μ

m², said second interconnection layer connecting said second resistor element to one of the active layers of said MOS type transistor (Q3).

12. An input protective apparatus for a semiconductor device as recited in claim 1, wherein

said second resistor element (R2) is diffusion resistance comprising a stripe-like diffusion layer having a width of more than 50 μ

m, an area of a contact region between a first interconnection layer an said second resistor element (R2) is more than 250 μ

m², said first interconnection layer connecting said second resistor element (R2) to said input terminal, and an area of a contact region between a second interconnection layer and said second resistor element is more than 300 μ

m², said second interconnection layer connecting said second resistor element to one of the active layers of said MOS type transistor, and the spacing between peripheral portions of each of said contact regions and said active layer (111) is more than 5μ

m.

13. An input protective apparatus for a semiconductor device in accordance with claim 1 wherein said relationships between resistance values is selected to establish time constants for discharging surge pulses from an external source.

14. An input protective apparatus as recited in claim 10 wherein said contact areas, width and spacing, and said resistance values, are selected to establish time constants for discharging surge pulses from an external source.

16. An input protective apparatus as recited in claim 1 wherein t₃ designates a time period required for punch through of said MOS transistor (Q4), t₂ designates a propagation time to said semiconductor device (Q3) to be protected of a pulse appearing at said external terminal (11) and t₁ designates a propagation time to ground of a pulse applied to said external terminal (11), wherein said resistance values are selected to establish a relationship t₂ -t₁ >

t₃.

17. An input protective apparatus as recited in claim 16 wherein said relationship between said values of said first and second resistance values is such as to establish a relationship between t₁ and t₂ wherein t₂ >

>

t₁.

18. An input protective apparatus as recited in claim 13 wherein said relationships between said resistance values is such as to establish a relationship between said time constants wherein t₂ >

>

t₁,

where t₂ designates a propagation time to said semiconductor device (Q3) to be protected of a pulse appearing at said external terminal (11) and t₁ designates a propagation time to ground of a pulse applied to said external terminal (11).

19. An input protective apparatus as recited in claim 18 wherein said relationships between said resistance values is such as to establish a relationship between said time constants wherein t₂ -t₁ >

t₃,

wherein t₃ designates a time period required for punch through of said MOS transistor (Q4).

15. An input protective apparatus for a semiconductor device (Q3), comprising an MOS transistor (Q4) having one active layer connected through a first resistor element (R1) to an input node of said device (Q3) and another active layer connected to a ground terminal of said device, a gate of said MOS transistor formed with a thick oxide insulating film and connected to said ground terminal,

which further comprises an external terminal (11) receiving an input signal to be applied to the input node of said semiconductor device (Q3) and a second resistor element (R2) connected between said external terminal (11) and one of the active layers of said MOS transistor (Q4),

a resistance value R₁ of said first resistor element (R1) and a resistance value R₂ of said second resistor element (R2) having the relation R₁ >

R₂, and said MOS type transistor being formed such that an on-resistance R₃ thereof satisfies a relation R₃ <

<

R₂.