Method of making a flexible tester surface for testing integrated circuits

• US 5,020,219 A
• Filed: 11/14/1989
• Issued: 06/04/1991
• Est. Priority Date: 05/16/1988
• Status: Expired due to Term

• Current Assignee: ELM TECHNOLOGY CORPORATION
• Original Assignee: Glenn J. Leedy
• Inventors: Leedy, Glenn J.
• Primary Examiner(s): Hall, Carl E.
• Assistant Examiner(s): Arbes, Carl J.
• Application Number:
  US07/436,395
• Time in Patent Office: 567 Days
• Field of Search: 29/407, 29/846, 29/832, 29/825, 204/15, 324/158 P, 430/316, 430/317, 430/318, 430/319, 437/8
• US Class Current: 29/846
• CPC Class Codes: G01R 1/07307 with individual probe elements, e.g. needles, cantilever beams or bump contacts, fixed in relation to each other, e.g. bed of nails fixture or probe card
• CPC Class Codes: G01R 1/0735 arranged on a flexible frame or film
• CPC Class Codes: G01R 31/2831 Testing of materials or semi-finished products, e.g. semiconductor wafers or substrates G01R31/318511 takes precedence; testing during manufacture H01L22/00
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G03F 7/70466 Multiple exposures, e.g. combination of fine and coarse exposures, double patterning or multiple exposures for printing a single feature stitching G03F7/70475
• CPC Class Codes: G03F 7/70658 Electrical testing
• CPC Class Codes: G11C 29/006 at wafer scale level, i.e. wafer scale integration [WSI]
• CPC Class Codes: H01L 22/22 Connection or disconnection of sub-entities or redundant parts of a device in response to a measurement testing and repair of stores after manufacture including at wafer scale G11C29/00; fuses per se H01L23/525
• CPC Class Codes: H01L 2924/15192 Resurf arrangement of the internal vias
• CPC Class Codes: Y10T 29/4913 Assembling to base an electrical component, e.g., capacitor, etc.
• CPC Class Codes: Y10T 29/49155 Manufacturing circuit on or in base

Abstract

Each transistor or logic unit on an integrated circuit wafer is tested prior to interconnect metallization. By CAD means, the transistor or logic units placement net list is revised to substitute redundant defect-free logic units for defective ones. Then the interconnect metallization is laid down and patterned under control of a CAD means. Each die in the wafer thus has its own interconnect scheme, although each die is functionally equivalent, and yields are much higher than with conventional testing at the completed circuit level.

The individual transistor or logic unit testing is accomplished by a specially fabricated flexible tester surface made in one embodiment of several layers of flexible silicon dioxide, each layer containing vias and conductive traces leading to thousands of microscopic metal probe points on one side of the test surface. The probe points electrically contact the contacts on the wafer under test by fluid pressure. The tester surface traces are then connected, by means of multiplexers, to a conventional tester signal processor.

Claims

1. A method of making an integrated circuit tester surface comprising the steps of:

forming at least one layer of flexible material on a surface of substrate;

forming a plurality of conductive vias in each of said layers;

depositing a thin film of conductive metal on each of said layers and in said vias;

patterning said thin film to form conductive traces;

releasing said layer from said substrate; and

forming conductive probe points at said vias.

2. The method of claim 1, wherein said step of forming said layer of flexible material comprises chemical vapor deposition of low stress silicon dioxide.

3. The method of claim 1, further comprising the step of affixing a rigid annular support to said thin film of conductive metal, prior to said releasing step.

4. The method of claim 1, wherein said step of forming said probe points comprises electrolyzation.

5. The method of claim 1, wherein said probe points are formed of a material selected from the group consisting of gold, tungsten, titanium, copper, nickel, chromium and aluminum.

6. The method of claim 1, further comprising the step of depositing a release agent on said substrate surface prior to said step of depositing the first said layer of flexible material.

7. The method of claim 1, wherein said step of releasing said layer from said substrate comprises the step of etching away said substrate by chemical means.

8. The method of claim 1, further comprising the step of refurbishing said probe points.

9. The method of claim 8, wherein said step of refurbishing comprises the steps of:

dissolving said probe points in acid; and

forming conductive probe points at said vias.

10. The method of claim 1, wherein said probe points are formed of an elastomeric material.

11. The method of claim 1, wherein said probe points are formed of a conductive elastomeric material.

12. The method of claim 1, wherein said flexible material is silicon nitride.

13. The method of claim 1, wherein said flexible material is a polymer.

14. The method of claim 1, further comprising the step of forming a depression in the surface of the substrate prior to forming the layer of flexible material.

15. The method of claim 1, further comprising the step of forming logic circuitry on the surface of the substrate prior to forming the layer of flexible material.

16. The method of claim 1, wherein said probe points are formed of two conductive materials.

17. The method of claim 1, wherein the step of forming conductive probe points comprises the step of forming probe points having a diameter of about 2 to 4 microns.

18. The method of claim 1, wherein the step of forming probe points comprises the step of forming more than one thousand probe points.

19. The method of claim 1, wherein the tester surface has a thickness of no greater than 15 microns.

20. The method of claim 11, wherein each of the conductive probe points measures no greater than 4 mils×

4 mils.

21. The method of claim 1, further comprising the steps of:

forming an insulating layer over the thin film of conductive metal; and

forming a second thin film of conductive metal over the insulating layer.

22. The method of claim 1, further comprising the step of electrically connecting the conductive traces to integrated circuitry.

23. The method of claim 1, further comprising the step of mounting integrated circuits on the thin film of conductive metal and connecting the integrated circuits to the conductive traces.

24. A method of making an integrated circuit tester surface comprising the steps of:

forming a plurality of cavities in a surface of a substrate;

forming logic circuitry on the surface of the substrate;

forming a depression in a center portion of the substrate;

forming a thin film of metal on the surface of the substrate and thereby filling each of the cavities;

forming a layer of flexible material on the thin film of metal;

removing at least a portion of the substrate; and

attaching the layer of flexible material to a support.

25. The method of claim 24, further comprising the steps of:

forming a second thin film of conductive metal on the flexible material; and

patterning the second thin film to form conductive traces.

26. The method of claim 24, further comprising the step of forming an insulating layer on the surface of the substrate underlying the thin film of metal.

27. The method of claim 24, further comprising the steps of interconnecting the logic circuitry to the portions of the thin film of metal filling each of the cavities in the same processing step in which the thin film of metal is formed.