Method of fabricating cross-point lightly-doped drain-source trench transistor

• US 5,021,355 A
• Filed: 05/18/1990
• Issued: 06/04/1991
• Est. Priority Date: 05/22/1989
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Dhong, Sang H., Hwang, Wei, Lu, Nicky C.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): WILCZEWSKI, MARY A
• Application Number:
  US07/513,711
• Time in Patent Office: 382 Days
• Field of Search: 435/35, 435/40, 435/41, 435/44, 435/52, 435/203, 435/233, 435/241
• US Class Current: 438/270
• CPC Class Codes: H01L 21/2236 from or into a plasma phase
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/7834 with a non-planar structure, e.g. the gate or the source or the drain being non-planar
• CPC Class Codes: H10B 12/01 Manufacture or treatment
• CPC Class Codes: H10B 12/39 the capacitor and the transistor being in a same trench
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices

Abstract

A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region in a wafer including an epitaxial layer on a substrate. A first, heavily doped drain region and bit line element is formed around the trench on the surface of the well, and a second, lightly-doped drain region is formed proximate to the first drain region and self-aligned to the trench sidewalls. A source region is located beneath the trench, which is filled with polysilicon, above which is gate and further polysilicon forming a transfer wordline. The well region at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.

Claims

1. A process for fabricating a self-aligned, lightly-doped drain/source field effect trench transistor device comprising the steps of:

Step

     1) on semiconductor substrate material having a layer of epitaxial material thereon, implanting dopants to form a retrograde well region in said epitaxial material,

Step

     2) forming oxide isolation regions in the surface of said well region and implanting dopants between said isolation regions to form a diffusion region to provide first drain junction regions,

Step

     3) etching a vertical trench through said diffusion region into said well region,

Step

     4) implanting dopants into the vertical sides of said trench using a low angle oblique ion implantation technique,

Step

     5) forming layers of silicon nitride masking material on the vertical sidewalls of said trench extending below the level of said diffusion region formed in Step 2,

Step

     6) forming self-aligned and lightly doped second drain junction regions on the sidewalls of said vertical trench above said silicon nitride mask layers and form buried source junction below the bottom of said trench by using said low angle oblique ion implantation technique,

Step

     7) growing oxide on said recessed oxide regions and on the bottom of said trench over said source junction,

Step

     8) removing said silicon nitride mask layer from said vertical trench sidewalls and growing a thin gate oxide on said vertical trench sidewalls, and

Step

     9) filling said trench with polysilicon and depositing polysilicon over said filled trench and over said recessed oxide regions and well surface to form transfer gate and wordline elements.

2. A process according to claim 1 wherein in Step 1) said substrate is formed of n+ type semiconductor material, said epitaxial layer is formed of n- type semiconductor and said well region is doped with p- type dopants.

3. A process according to claim 2 wherein in Step 2) said first drain junction diffusion region is heavily doped with n++ type dopants.

4. A process according to claim 3 wherein in Step 6) said lightly-doped second drain junctions are formed with n+ type dopants.

5. A process according to claim 4 wherein said dopants implanted into the vertical sidewalls of said trench in Step 4) are p+ dopants to control the n-channel threshold voltage of said transistor device.