Control circuit for floating gate four-quadrant analog multiplier

• US 5,021,693 A
• Filed: 03/28/1990
• Issued: 06/04/1991
• Est. Priority Date: 04/05/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Shima, Takeshi
• Primary Examiner(s): Hudspeth, David
• Assistant Examiner(s): TRAN, TOAN V
• Application Number:
  US07/500,309
• Time in Patent Office: 433 Days
• Field of Search: 307/495, 307/570, 307/494, 307/530, 307/201, 365/185, 365/207, 365/208, 364/807, 357/25.5
• US Class Current: 327/357
• CPC Class Codes: G06N 3/065 Analogue means
• CPC Class Codes: H03F 3/45076 characterised by the way of implementation of the active amplifying circuit in the differential amplifier

Abstract

Disclosed is an electronic circuit comprising commonly connecting the gate end of a first transistor having a floating gate and the source end and the drain end of a second transistor having a floating gate to a first control input terminal, and commonly connecting the source end and the drain end of the first transistor and the normal gate end of the second transistor to a second control input terminal. The electronic circuit can repeatedly set and maintain accumulation charge amounts of the respective floating gates of the first and the second transistor at predetermined values. Also disclosed is an electronic circuit including the above electronic circuit, and further comprising commonly connecting the respective souce ends of a third and a fourth transistor to a first terminal to compose a first differential couple, providing a current source between the first terminal and a power source end or and earthed end, connecting the floating gates of the first and the third transistor together, connecting the floating gates of the second and the fourth transistor together, connecting the normal gate end of the third transistor to a first positive input terminal, and connecting the normal gate end of the fourth transistor to a first negative input terminal. The so-composed electronic circuit can repeatedly set and maintain threshold values in differential amplification at respective predetermined values. Further disclosed is an analog multiplication circuit comprising combination of these electronic circuits and an amplification circuit, which can repeatedly set and maintain weight concerning multiplication factors at predetermined values.

Claims

1. An electronic circuit, comprising:

a first transistor having a floating gate;

a second transistor having a floating gate;

commonly connecting the normal gate end of the first transistor and the source end and the drain end of the second transistor to a first control input terminal; and

commonly connecting the source end and the drain end of the first transistor and the normal gate end of the second transistor to a second control input terminal, so that accumulation charge amounts in the respective floating gates of the first and the second transistor can be controlled by controlling input to be given to the first and the second control input terminal.

4. An electron circuit according to claim 1, wherein

the first and the second transistor are respectively composed of a MOS transistor.

2. A differential amplification circuit, comprising:

commonly connecting the normal gate end of a first transistor having a floating gate and the source end and the drain end of a second transistor having a floating gate to a first control input terminal;

commonly connecting the source end and the drain end of the first transistor and the normal gate end of the second transistor to a second control input terminal;

commonly connecting the respective source ends of a third and a fourth transistor respectively having floating gates to a first terminal to compose a first differential couple;

providing a current source between the first terminal and a power source end or an earthed end;

connecting the floating gates of the first and the third transistor together;

connecting the floating gates of the second and the fourth transistor together;

connecting the normal gate end of the third transistor to a first positive input terminal; and

connecting the normal gate of the fourth transistor to a first negative input terminal.

5. A differential amplification circuit according to claim 2, wherein

the first, the second, the third and the fourth transistor are respectively composed of a MOS transistor.

7. A differential amplification circuit according to claim 2, wherein

the third and the fourth transistor are composed of a transistor without the normal gate end.

3. An analog multiplication circuit, comprising:

commonly connecting the normal gate end of a first transistor having a floating gate and the source end and the drain end of a second transistor having a floating gate to a first control input terminal;

commonly connecting the source end and the drain end of the first transistor and the normal gate end of the second transistor to a second control input terminal;

commonly connecting the respective source ends of a third and a fourth transistor respectively having floating gates to a first terminal to compose a first differential couple;

providing a current source between the first terminal and a power source end or an earthed end;

connecting the floating gates of the first and the third transistor together;

connecting the floating gates of the second and the fourth transistor together;

connecting the normal gate end of the third transistor to a first positive input terminal;

connecting the normal gate of the fourth transistor to a first negative input terminal;

commonly connecting the source ends of a pair of a fifth and a sixth transistor to a second terminal to compose a differential couple;

also connecting the drain end of the third transistor to the second terminal;

commonly connecting the source ends of a seventh and an eighth transistor to a third terminal to compose a third differential couple;

also connecting the drain end of the fourth transistor to the third terminal;

commonly connecting the respective normal gates of the fifth and the eighth transistor to a second positive input terminal;

commonly connecting the respective normal gates of the sixth and the seventh transistor to a second negative input terminal;

commonly connecting the respective drain ends of the fifth and the seventh transistor to a positive output terminal; and

commonly connecting the respective drain ends of the sixth and the eighth transistor to a negative output terminal.

6. An analog multiplication circuit according to claim 3, wherein

the first, the second, the third and the fourth transistor are respectively composed of a MOS transistor.

8. An analog multiplication circuit according to claim 3, wherein

the third and the fourth transistor are composed of a transistor without the normal gate end.