Process for driving an alternating-current motor and an alternating current motor which can be driven in accordance with this process

• US 5,021,726 A
• Filed: 12/04/1989
• Issued: 06/04/1991
• Est. Priority Date: 12/07/1988
• Status: Expired due to Fees

• Current Assignee: EMB Werke GmbH & Company
• Original Assignee: EBM Elektrobau Mulfingen GmbH & Company
• Inventors: Reinhardt, Wilhelm, Schultz, Karl-Heinz
• Primary Examiner(s): Ro, Bentsu
• Application Number:
  US07/445,986
• Time in Patent Office: 547 Days
• Field of Search: 318/138, 318/254, 318/439, 318/599, 318/807, 318/808, 318/810, 318/811
• US Class Current: 318/811
• CPC Class Codes: H02P 27/08 with pulse width modulation

Abstract

Method and apparatus for driving an alternating-current motor. A sinusoidal supply AC voltage is rectified into a pulsating, unsmoothed DC voltage, with sinusoidal half waves and from this DC voltage an alternating-current motor voltage is produced by means of controllable polarity reversal. The pulse width of this alternating-voltage of the motor can be modulated. The polarity reversal takes place in accordance with the supply frequency in such a way that the AC voltage of the motor is essentially composed of the sinusoidal half waves of the pulsating DC voltage. For this purpose, the motor speed can be altered by changing the AC voltage of the motor with a constant timing frequency, lying outside the range of audibility, into pulse-width modulatable voltage pulses.

Claims

1. Method for driving an AC motor with speed control, comprising the steps of:

pulse timing an AC motor voltage (U_M) into pulse-width modulatable voltage pulses with a constant clock pulse frequency lying outside the hearing range;

controlling the motor speed by pulse-width modulation of said voltage pulses;

obtaining the AC motor voltage (U_M) indirectly from a sinusoidal AC supply voltage (U_N) by rectifying said supply voltage (U_N) into a pulsating, unsmoothed DC voltage (U_A1) having sinusoidal half-waves; and

controlling the polarity reversal of said DC voltage in accordance with the frequency of the AC supply voltage by means of two time overlap-free output signals (U_K1, U_K2) obtained from said AC supply voltage, so that said motor-voltage (U_M) is essentially composed of the sinusoidal half-waves of said pulsating DC-voltage (U_A1).

2. The method in accordance with claim 1 characterized by controlling the polarity reversal of the DC voltage (U_A1) from the AC supply voltage (U_N) by deriving a positive voltage signal (U_P1) which is cophasal with the AC supply voltage, and deriving a negative voltage signal (U_N2) which is also cophasal with the AC supply voltage (U_N), wherein each of these derived voltage signals (U_P1, U_N2) has sinusoidal half waves, comparing the derived voltage signals with a constant reference voltage (U_ref1 U_ref2) and, on the basis of this comparison, producing said two overlap-free output signals (U_K1, U_K2)separated by contact breaks.

3. The method in accordance with claim 2, characterized by producing four control signals (S1, S2, S3, S4) in response to the two overlap-free output signals (U_K1, U_K2) such that at all times only two control signals each (S2, S4 or S1, S3) lie at a logical "1" potential, while each of the other control signals (S1, S3, or S2, S4) lie at the logical "0" potential.

4. The method in accordance with claim 3, characterized in that the control signals (S1, S2, S3, S4) are directed to the gate electrodes (G) of an output stage (4), which are in an H-bridge circuit arrangement, wherein the motor (2) is connected to the shunt arm of the H-bridge circuit.

5. The method in accordance with claim 3 or 4, characterized in that for the speed adjustment of the motor, one (S3;

S4) of the two control signals with the same potential (S1, S3 or S2, S4) is synchronized in a pulse-width modulatable manner.

6. The method in accordance with claim 5, characterized in that by comparing a sawtooth voltage (U_SZG) with an adjustable reference voltage (U_DZ), a timing output signal (U_K4) is produced which has a logical "0" potential when the reference voltage (U_DZ) is greater than the sawtooth voltage (U_SZG) and which has a logical "1" potential when the reference voltage (U_DZ) is smaller than the sawtooth voltage (U_SZG), and maintaining the control signals (S3 and S4) at the "0" potential through the two overlap-free output signals (U_K1, U_K2) when the timing output signal (U_K4) has a logical "1" potential.

7. The method in accordance with claim 6, characterized in that the reference voltage (U_DZ) is selectively adjustable so as to vary the operating speed of the motor.

8. The method in accordance with claim 6, characterized in that during the staring of the motor, the reference voltage (U_DZ) is automatically changed to follow the voltage charge of a capacitor (U_C9).

9. The method in accordance with claim 6, characterized in that when a predetermined disturbance variable occurs, a disturbance variable voltage signal with a logical "0" potential is produced, which then represents the reference voltage (U_DZ), so that the timing output signal (U_K4) has the logical "1" potential at all times in response to the disturbance variable voltage signal.

10. The method in accordance with claim 9, characterized by determining the motor current by measuring the voltage decline (U_R19) at a resistance connected to the motor and comparing this voltage decline (U_R19) with an adjustable current-reference voltage (U_P3), wherein the disturbance variable voltage signal is produced when the voltage decline (U_R19) is greater than said current-reference voltage (U_P3).

11. The method in accordance with claim 9, characterized in that the disturbance variable is temperature, the temperature is determined by measuring the voltage drop (Utemp) at a temperature-dropping resistor (N_TC), and this voltage drop is compared, on the one hand, with a higher temperature-reference voltage (U_ref3) and, on the other hand, with a lower temperature-reference voltage (U_ref4), wherein the disturbance variable voltage signal is produced when the voltage drop (U_temp) of the temperature-dropping resistor (N_TC) becomes smaller than the lower temperature reference voltage (U_ref4) through heating, and wherein the disturbance variable voltage signal is automatically cancelled when the voltage drop (U_temp) is again greater than the higher temperature reference voltage (U_ref3) following cooling.

12. A speed controller for a controllable alternating-current motor with at least one motor winding comprises a supply voltage bridge rectifier circuit, an output stage connected with the rectifier circuit and with electronic switching elements provided in the output stage, wherein the motor winding is connected to one bridge shunt arm of the output stage and with a driver arrangement which is connected with the output stage and which drives the electronic switching elements and with a pulse-width modulator, connected with the switching elements, characterized in that:

the rectifier circuit (6) has outputs (A1, A2) which are connected with inputs (E1, E2) of the output stage (4) so that said rectifier circuit rectifies AC supply voltage and produces an unsmoothed, pulsating Dc voltage (U_A1) with sinusoidal half waves is present at the inputs (E1, E2), the driver arrangement (10,

     12) drives the electronic switching elements (T3 to T6) in accordance with the frequency of the ac supply voltage in such a way that at the outputs (M1, M2) of the output stage (4), connected with the motor winding (2), a motor AC voltage (U_M) is present which is composed of the sinusoidal half waves of the pulsating direct current voltage (U_A1), and wherein a control electrode (G) of one switching element in each (T5;

T6) of the switching elements, which are driven in paris, indirectly connected with the pulse-width modulator (16), which synchronizes at a constant, pulse-width modulatable timing frequency, so as to provide selective speed control of the motor.

13. A speed controller in accordance with claim 12, characterized in that the timing frequency of the pulse-width modulator (16) is ≧

20 k_Hz.

14. A speed controller in accordance with claim 12 or 13, characterized in that the driver arrangement has a driver circuit (10) with a first comparator (IC3a) and a second comparator EC3b), means providing a positive reference voltage (U_ref1) at the inverting input of the first comparator (IC3a), means providing a positive voltage (U_P1) at the noninverting input of the second comparator, the positive voltage (U_P1) being derived from and cophasal with the AC supply voltage (U_N) having sinusoidal half waves, and means providing a negative reference voltage (U_ref2) at the noninverting input of the second comparator (IC3b), means providing at the inverting input of the second comparator a voltage (U_N2) which is derived from the AC supply voltage (U_N) and which is in phase with the AC supply voltage and is negative, consisting of sinusoidal half waves, wherein the amount of the reference voltages (U_ref1, U_ref2) is in each case substantially smaller than the amount of the peak value of the respectively derived voltage (U_P1, U_N2).

15. A speed controller in accordance with claim 14, characterized in that the driver arrangement has a connection circuit (12) with two inputs (Y1, Y2), each of which is connected with an output of one of the two comparators (IC3a, IC3b) of the driver circuit (10) via a line (K1, K2), wherein the connection circuit (12) has four outputs (Z1 to Z4) for control signals (S1 to S4), which are connected with the control electrodes (G) of the electronic switching elements (T3 to T6) of the output stage (4).

16. A speed controller in accordance with claim 15, characterized in that in at least two outputs (Z1, Z2) of the connection circuit (12), there is one driver stage (TR) for electrical isolation between the connection circuit (12) and the output stage (4).

17. A speed controller in accordance with claim 15, characterized in that the connection circuit (12) has two additional inputs (Y3, Y4), which influence at least two of the outputs (Z3, Z4) in such a way, that with a logical "0" potential at the additional inputs (Y3, Y4), the control signals (S3, S4) at these outputs (Z3, Z4) are always equal to logical "0".

18. A speed controller in accordance with claim 17, characterized in that the additional inputs (Y3, Y4) of the connection circuit (12) are each connected with ground (A2) via the collector/emitter lines of two transistors (T1, T2), wherein the bases of the two transistors (T1, T2) are connected with a common driver line (S5).

19. A speed controller in accordance with claim 18, characterized in that the common driver line (S5) is connected with the output of a rpm comparator (IC8b), forming the pulse-width modulator (16), wherein the noninverting input of the rpm comparator is connected with an output of a sawtooth generator (32) and its inverting input is connected with a central switching point (B).

20. A speed controller in accordance with claim 19, characterized in that the central switching point (B) is connected with a friction contact of a speed-adjusting potentiometer (P2).

21. A speed controller in accordance with claim 19, characterized in that the central switching point (B) is linked with a connection for an external control voltage (U_E).

22. A speed controller in accordance with claim 19, characterized in that the central switching point (B) is connected with a capacitor (C9) operative to produce a rising voltage for controlling a gradual starting arrangement (44) of the motor.

23. A speed controller in accordance with claim 19, characterized in that the central switching point (B) is connected with the output of a current comparator (IC8a), forming a current-limiting arrangement (STB), at the inverting input of which a voltage (Ur19) is present, which is tapped at a resistance (R19) arranged in the motor current circuit and proportional to the motor current, and at the noninverting input of which a current-reference voltage (U_P3) is present which is selectively adjustable via a current-adjusting potentiometer (P3).

24. A speed controller in accordance with claim 19, characterized in that the central switching point (B) is connected with the output of an overtemperature shutoff arrangement (50).

25. A speed controller in accordance with claim 24, characterized in that the overtemperature shutoff arrangement (50) has a first temperature comparator (IC8c) and a second temperature comparator (IC8d), wherein at each of the inverting inputs of these comparators, a voltage (U_temp) is present which drops at a temperature-dropping resistor (NTC) and wherein, at the noninverting input of the first temperature comparator (IC8c), a first reference voltage (U_ref3) is present and at the noninverting input of the second temperature comparator (IC8d), a second reference voltage (U_ref4) is present, whereby the first reference voltage (U_ref3) is greater than the second reference voltage (U_ref4) and, during normal operation of the motor, the voltage (U_temp) at the temperature-dropping resistor (NTC) is greater than the first reference voltage (U_ref3).

26. A speed controller in accordance with claim 25, characterized in that the inverting input of the second temperature comparator (IC8d) is connected with ground (A2) via the collector/emitter line of a blocking transistor (T7), wherein the base of the blocking transistor (T7) is connected, on the one hand, with the output of the first temperature comparator (IC8c) and, on the other hand, with the output of the second temperature comparator (IC8d).

27. A speed controller in accordance with claim 25 characterized in that the output of the second temperature comparator (IC8d) is connected with the base of a shutoff transistor (T8), the collector/emitter line of which lies between the ground (A2) and the output of the overtemperature shutoff arrangement (50), this output being connected with the central switching point (B).