Interactive real-time video processor with zoom pan and scroll capability

• US 5,021,772 A
• Filed: 10/05/1989
• Issued: 06/04/1991
• Est. Priority Date: 11/20/1986
• Status: Expired due to Fees

• Current Assignee: Her Majesty The Queen In Right of Canada As Represented By The Minister of National Defence
• Original Assignee: Drumoyne Investments, Ltd.
• Inventors: King, Stephen J., Magee, Lochlan E.
• Primary Examiner(s): Oberley, Alvin
• Application Number:
  US07/462,868
• Time in Patent Office: 607 Days
• Field of Search: 340/723, 340/703, 340/724, 340/747, 340/744, 340/791, 340/793, 340/799, 340/726, 358/22, 358/180
• US Class Current: 345/632
• CPC Class Codes: G09B 9/003 for military purposes and tactics
• CPC Class Codes: G09B 9/302 the image being transformed by computer processing, e.g. updating the image to correspond to the changing point of view
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: H04N 5/262 Studio circuits, e.g. for mixing, switching-over, change of character of image, other special effects ; Cameras specially adapted for the electronic generation of special effects

Abstract

A video processor used in conjunction with commercial video products provides realistic visual imagery and a dynamic interactive capability. The outputs from three video digitizers, one for each of the primary colours red, green and blue (RGB) of a composite video signal, are stored in high speed, serial access memory devices. The output of the memory devices is converted to an analog signal for an ordinary RGB monitor. Image content can be transformed in real-time via microprocessor control of selected data in the memory devices, encoding and retrieval circuits permitting a portion of the original video signal to completely fill a normal RGB monitor. As well, computer generated imagery can be superimposed upon the video background and the background can be altered to achieve special visual effects.

Claims

1. In an interactive video processor for processing image data corresponding to video scan lines derived form scanning an image, said processor comprising:

sampling means for sampling the image data,

storing means for storing the sampled image data, at a given rate of storage, in successive memory addresses of said storing means,

retrieving means for retrieving the stored image data,

processing means for processing the retrieved image data, and

display means for displaying the image originally scanned;

the improvement comprising pan circuit means for delaying the storage of the sampled image data relative to the start of each video scan line by an amount of time appropriate to achieve a desired horizontal displacement of the displayed image, and scroll circuit means for initiating data retrieval at a memory address appropriate to the video scan line which is to appear at the top of the display of the image so as to achieve vertical displacement of the displayed image; and

wherein said retrieving means retrieves the image data at a rate equal to a predetermined fraction of the rate of storage of the image data, and said display means displays the image data corresponding to each video scan line twice so as to produce a display of the image which is effectively magnified by a predetermined factor.

2. In the processor of claim 1, further comprising selecting means responsive to an operator selection input for selecting the magnified image or an unmagnified image for display.

3. In the processor of claim 1, wherein said storing means comprises two memory modules and data entry means for storing the sampled image data into alternative ones of said memory modules during successive data entry cycles, said retrieving means simultaneously retrieving the image data from said memory module other than said memory module in which the image data are being stored during the successive data entry cycles.

4. In the processor of claim 1, further comprising additional memory means for storing other data, said processing means combining the image data retrieved from said storing means with the other data.

5. In the processor of claim 1, further comprising additional processing means for modifying the other data stored in additional memory means.

6. In the processor of claim 1, further comprising a composite colour decoder including an input access for a video signal source and an output access for each primary colour signal, said output access providing a signal comprising the image data sampled by said sampling means.

7. In the processor of claim 1, further comprising colour look-up table means for selectively changing the outcome of combinations of the image data from said storing means with the other data.

8. In the processor of claim 1, wherein the image data are provided to said sampling means by a videodisc player.

9. In the processor of claim 1, wherein the image data are provided to said sampling means by a videocassette recorder.

10. In the processor of claim 1, wherein the image data are provided to said sampling means by a radio frequency tuner.

11. In the processor of claim 1, wherein said pan circuit means comprises a pan register for receiving horizontal displacement data and a pan counter connected to said pan register for receiving the horizontal displacement data from said pan register.

12. In the processor of claim 11, wherein said scroll circuit means comprises a scroll register for receiving vertical displacement data and a scroll counter connected to said scroll register for receiving the vertical displacement data from said scroll register.

13. In the processor of claim 12, wherein said scroll counter produces a counter output, and wherein said storing means comprises a row counter, and further comprising increment gate means connected between said scroll counter and said storing means and responsive to said counter output for incrementing the row counter of said storing means during a vertical sync interval of said display means until a desired scroll value is reached as indicated by the counter output of said scroll counter.

14. In the processor of claim 13, wherein said storing means receives a write enable signal and a serial clock signal, and wherein said pan counter delays reception of the write enable signal and the serial clock signal by said storing means.

15. In the processor of claim 2, wherein said storing means receives a write enable signal and a serial clock signal, and wherein said pan counter delays reception of the write enable signal and the serial clock signal by said storing means.

16. In the processor of claim 11, wherein said storing means receives a write enable signal and a serial clock signal, and wherein said pan counter delays reception of the write enable signal and the serial clock signal by said storing means.

17. In the processor of claim 11, wherein said scroll counter produces a counter output, and wherein said storing means comprises a row counter, and further comprising increment gate means connected between said scroll counter and said storing means and responsive to said counter output for incrementing the row counter of said storing means during a vertical sync interval of said display means until a desired scroll value is reached as indicated by the counter output of said scroll counter.