MOS semiconductor device with an inverted U-shaped gate
First Claim
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1. A metal oxide semiconductor device, having a gate formed in an inverted U-shaped recess with a depth and width of said recess exceeding the limited thickness of the semiconductor layer applied to form said gate, comprising:
- a semiconductor substrate having an inverted U-shaped recess formed of an inside channel of a first depth below the surface of said substrate connecting two outside channels whose depth below said surface substantially exceeds said first depth of said inside channel;
an insulative film covering the surface of said recess;
a gate formed by said limited thickness of semiconductor material within said recess in contact with said insulative film and filling said inside and outside channels to substantially said substrate surface;
a base layer formed at the surface of said substrate adjacent to and in contact with said insulative film and having a thickness less than the depth of said outside channels; and
a source layer at the surface of said base layer adjacent to and in contact with said insulative film and having a thickness less than the thickness of said base layer,whereby a vertical conducting path adjacent to said insulating film is formed upon biasing said gate, and the semiconductor device is enabled to operate with a higher area utilization rate for main current flow.
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Abstract
Provided is a metal oxide semiconductor with an inverted U-shaped recess formed therein, the recess having two relatively deep outside channels and an interconnecting relatively shallow channel. The recess is filled with polycrystalline silicon gate material, and when biased, a conductive region is formed alongside an outside channel. Also provided also is a method of forming such an inverted U-shaped recess in a metal oxide semiconductor.
24 Citations
9 Claims
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1. A metal oxide semiconductor device, having a gate formed in an inverted U-shaped recess with a depth and width of said recess exceeding the limited thickness of the semiconductor layer applied to form said gate, comprising:
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a semiconductor substrate having an inverted U-shaped recess formed of an inside channel of a first depth below the surface of said substrate connecting two outside channels whose depth below said surface substantially exceeds said first depth of said inside channel; an insulative film covering the surface of said recess; a gate formed by said limited thickness of semiconductor material within said recess in contact with said insulative film and filling said inside and outside channels to substantially said substrate surface; a base layer formed at the surface of said substrate adjacent to and in contact with said insulative film and having a thickness less than the depth of said outside channels; and a source layer at the surface of said base layer adjacent to and in contact with said insulative film and having a thickness less than the thickness of said base layer, whereby a vertical conducting path adjacent to said insulating film is formed upon biasing said gate, and the semiconductor device is enabled to operate with a higher area utilization rate for main current flow. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Current AssigneeFuji Electric Company Limited (Fuji Electric Systems Company Limited)
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Original AssigneeFuji Electric Company Limited (Fuji Electric Systems Company Limited)
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InventorsUeno, Katsunori
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Primary Examiner(s)James, Andrew J.
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Assistant Examiner(s)Deal, Cynthia S.
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Application NumberUS07/475,713Time in Patent Office483 DaysField of Search357/23.4, 357/23.5, 357/23.6US Class Current257/330CPC Class CodesH01L 29/4236 within a trench, e.g. trenc...H01L 29/66348 with a recessed gateH01L 29/7813 with trench gate electrode,...
