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Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof

  • US 5,021,848 A
  • Filed: 03/13/1990
  • Issued: 06/04/1991
  • Est. Priority Date: 03/13/1990
  • Status: Expired due to Fees
First Claim
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1. A method of constructing a small tunnel dielectric area self aligned to an electrically floating, conductive gate, said method comprising the steps of:

  • forming a first floating, conductive gate on a first dielectric layer on a semiconductor region;

    depositing a second dielectric film over said floating gate;

    forming a sealing second dielectric film at the sidewall of said first floating gate by anisotropic etching of said second dielectric film;

    introducing impurity into said semiconductor region to form a buried doped region;

    forming a tunnel dielectric on said buried doped region;

    removing said sealing second dielectric film from the sidewall of said first floating gate;

    depositing an add-on conductive film of the same material as said first floating gate over said tunnel dielectric and said floating gate;

    forming an add-on floating, conductive gate at the sidewall of said first floating gate by the anisotropic etching of said add-on conductive film, said add-on floating gate being shorted electrically to said first floating gate.

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