Electrically-erasable and electrically-programmable memory storage devices with self aligned tunnel dielectric area and the method of fabricating thereof

• US 5,021,848 A
• Filed: 03/13/1990
• Issued: 06/04/1991
• Est. Priority Date: 03/13/1990
• Status: Expired due to Fees

• Current Assignee: Te-Long Chiu
• Original Assignee: Te-Long Chiu
• Inventors: Chiu, Te-Long
• Primary Examiner(s): Larkins, William D.
• Application Number:
  US07/492,113
• Time in Patent Office: 448 Days
• Field of Search: 437/43, 437/44, 357/23.5, 365/185
• US Class Current: 257/317
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

The EEPROM has the selection device in series with the memory device having a floating gate disposed over the channel between the buried drain and the buried source, and insulated from the channel by 200 A to 1000 A of gate oxide, an add-on floating gate shorted electrically to the floating gate, and disposed over and insulated from the buried drain by 40 A to 150 A of tunnel dielectric, and a control gate disposed over and insulated from the floating gate. The improvement in the proposed version of the memory device in the EEPROM is that the tunnel dielectric area is very small and is self aligned to the floating gate.

Claims

1. A method of constructing a small tunnel dielectric area self aligned to an electrically floating, conductive gate, said method comprising the steps of:

forming a first floating, conductive gate on a first dielectric layer on a semiconductor region;

depositing a second dielectric film over said floating gate;

forming a sealing second dielectric film at the sidewall of said first floating gate by anisotropic etching of said second dielectric film;

introducing impurity into said semiconductor region to form a buried doped region;

forming a tunnel dielectric on said buried doped region;

removing said sealing second dielectric film from the sidewall of said first floating gate;

depositing an add-on conductive film of the same material as said first floating gate over said tunnel dielectric and said floating gate;

forming an add-on floating, conductive gate at the sidewall of said first floating gate by the anisotropic etching of said add-on conductive film, said add-on floating gate being shorted electrically to said first floating gate.

2. The method as set forth in claim 1, wherein said first floating, conductive gate and said add-on conductive film are doped poly silicon film.

3. The method as set forth in claim 2, wherein said second dielectric film is a silicon nitride film.

4. An electrically alterable, nonvolatile, floating gate type memory device, comprising a substrate of semiconductor material having a channel region of a first type of conductivity between a first and a second region of a second type of conductivity, formed at the surface of said semiconductor substrate, said channel region providing a region within the semiconductor capable of passing an electric current between said first and said second region, a first level of patterned conducting material, constituting said floating gate, extending over said channel region, substantially between said first and said second region and electrically insulated by means of a first layer of dielectric material from said semiconductor substrate and by means of a second layer of dielectric material from a second level of patterned conducting material, constituting a control gate, overlying said floating gate and which further includes

a tunnel area defined on the surface of one of said first and second regions of the semiconductor substrate, said tunnel area being bordered on one side by the base of a portion of the length of a side wall of said floating gate and being covered with a third layer of dielectric material thinner than said first layer of dielectric material;

a tapered, lateral, seamlike appendix of conducting material juxtaposed along said portion of the length of the side wall of said floating gate, the base of said juxtaposed, tapered, lateral, seamlike appendix of conducting material abutting on the surface of said third layer of dielectric material covering said tunnel area;

said seamlike appendix being electrically connected to said patterned first level of conducting material constituting said floating gate along the entire periphery of said floating gate.

5. The device of claim 4, wherein said third layer of dielectric material has a thickness of between 40 Angstroms and 150 Angstroms.

6. The device of claim 4, wherein said seamlike appendix and said patterned first level of conducting material are both composed of doped polycrystalline silicon.

7. The device of claim 4, wherein second type of conductivity is N type.

8. The device of claim 4, wherein said first layer of dielectric material and said third layer of dielectric material are oxide layers.

9. The device of claim 6, wherein said second type of conductivity is N type, and said polycrystalline silicon is doped N type.

10. The device of claim 5, wherein said first layer of dielectric material has a thickness of between 200 Angstroms and 1000 Angstroms.

11. The device of claim 4, further comprising a third region of second conductivity type, spaced from said one of said first and second regions which has a tunnel area on the surface thereof by a second channel region of first conductivity, with an access gate electrode overlying said second channel but spaced therefrom by a gate insulator.

12. A memory array having a plurality of electrically alterable, nonvolatile, floating gate type memory devices, each as defined in claim 11, wherein the devices are arranged in rows and columns in a matrix, with a word line extending along each row, the access gate electrodes of each memory device in a row being connected to a corresponding row word line, and with a bit line extending along each column, the third region of each memory device in a column being connected to the corresponding bit line.