Bit synchronization circuit
First Claim
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1. A bit synchronization circuit provided for an individual subscriber'"'"'s line in a telephone exchange system, comprising:
- latch means for receiving a plurality of clocks of different phases from a clock generating circuit provided in common to a plurality of bit synchronization circuits in said telephone exchange system, latching an input data signal transmitted thereto through said subscriber'"'"'s line in response to said plurality of clocks of different phases, and providing latched output signals corresponding to said plurality of clocks of different phases;
detecting means for receiving said latched output signals from said latch means, and comparing said latched output signals to detect a plurality of points at which a variation in phase of said input data signal occurs in a predetermined time period;
regenerative output selecting means for receiving a detecting signal representing whether a variation in phase of said input data signal is detected by said detecting means, and selecting a latched output signal among said plurality of latched output signals provided by said latch means; and
phasing means for phasing said latched output signal selected by said regenerative output selecting means.
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Abstract
A telephone exchange system has a plurality of bit synchronization circuit each provided for an individual subscriber'"'"'s line. A single clock generating circuit which generates a plurality of clocks is provided in common to the plurality of bit synchronization circuits. The bit synchronization circuit selects one clock of a phase suitable for regenerating an input data signal among the plurality of clocks applied thereto by the clock generating circuit, and regenerates and phases the input data signal by using the selected clock.
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Citations
8 Claims
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1. A bit synchronization circuit provided for an individual subscriber'"'"'s line in a telephone exchange system, comprising:
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latch means for receiving a plurality of clocks of different phases from a clock generating circuit provided in common to a plurality of bit synchronization circuits in said telephone exchange system, latching an input data signal transmitted thereto through said subscriber'"'"'s line in response to said plurality of clocks of different phases, and providing latched output signals corresponding to said plurality of clocks of different phases; detecting means for receiving said latched output signals from said latch means, and comparing said latched output signals to detect a plurality of points at which a variation in phase of said input data signal occurs in a predetermined time period; regenerative output selecting means for receiving a detecting signal representing whether a variation in phase of said input data signal is detected by said detecting means, and selecting a latched output signal among said plurality of latched output signals provided by said latch means; and phasing means for phasing said latched output signal selected by said regenerative output selecting means. - View Dependent Claims (2, 3, 4)
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5. A bit synchronization circuit provided for an individual subscriber'"'"'s line in a telephone exchange system, comprising:
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latch means for receiving n clocks of different phases and of a clock rate equal to 1/m (m=n/k, where k, n and m are integers) of a data signaling rate of an input data signal from a clock generating circuit provided in common to a plurality of bit synchronization circuits in said telephone exchange system, correspondingly latching said input data signal transmitted through said subscriber'"'"'s line in response to said clocks, and providing m sets of output signals each including k latch output signals corresponding to said clocks; detecting means for receiving one set of k latch output signals, and comparing said latch output signals to detect a plurality of points at which a variation in phase of said input data signal occurs in a predetermined time period; regenerative output selecting means for receiving a detecting signal representing whether a variation in phase of said input data signal is detected by said detecting means, and selecting m latched output signals among said n latched output signals on the basis of said detection signal; phasing means for phasing said m latched output signals selected by said regenerative output selecting means; and data signaling rate converting means for producing an output data signal of a data signaling rate m times that of input signals output by said phasing means by combining said phased m input signals output by said phasing means. - View Dependent Claims (6, 7, 8)
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Specification