Implantable cardiac device with dual clock control of microprocessor

• US 5,022,395 A
• Filed: 07/07/1989
• Issued: 06/11/1991
• Est. Priority Date: 07/07/1989
• Status: Expired due to Term

• Current Assignee: Cardiac Pacemakers Incorporated 4100 Hamline Avenue North St Paul MN
• Original Assignee: Cardiac Pacemakers Incorporated (Boston Scientific Corporation)
• Inventors: Russie, Renold J.
• Primary Examiner(s): Kamm, William E.
• Assistant Examiner(s): Schaetzle, Kennedy J.
• Application Number:
  US07/376,511
• Time in Patent Office: 704 Days
• Field of Search: 128/419 PG, 128/419 P
• US Class Current: 607/16
• CPC Class Codes: A61N 1/37 Monitoring; Protecting

Abstract

A microprocessor based implantable cardiac treatment device having first and second clocks. The first clock is a continuously running external clock of a relatively low frequency for controlling low power, uncomplicated operations of the device. The second clock runs at a much higher frequency for controlling the complex, high power operations of the microprocessor. Clock control circuitry is provided for activating the second clock only when it is determined that high power calculations are to be made by the microprocessor.

Claims

1. An implantable microprocessor cardiac based device comprising:

microprocessor means for determining one of a plurality of cardiac treatment therapies;

external clock means for continuously generating a clock signal of a first frequency;

auxiliary clock means for generating a clock signal of a second frequency for controlling said microprocessor means, said auxiliary clock means being capable of assuming an active state for generating said clock signal of said second frequency, and an inactive state whereby no clock signal is generated;

interrupt decision means for setting the state of said auxiliary clock means;

clock control means for triggering said auxiliary clock means to assume one of said active or inactive states under control of said interrupt decision means and said microprocessor means;

a plurality of timer means capable of producing as output, time-out signals to said interrupt decision means and said microprocessor means;

clock divider means for receiving as input said clock signal of said first frequency and generating as output a plurality of clock signals at a plurality of different frequencies to said plurality of timer means; and

means to synchronize said external clock means and said auxiliary clock means so that said plurality of timer means are in a stable state when the microprocessor means reads said time-out signals.

2. The device of claim 1, wherein said first frequency generated by said external clock means is substantially slower than the second frequency generated by said auxiliary clock means.

3. The device of claim 1, wherein said microprocessor means controls said clock control means to trigger said auxiliary clock means to assume said inactive state.

4. The device of claim 1, wherein said clock signal of said first frequency is 32 KHz and said clock signal of said second frequency is 1 MHz.

5. A microprocessor based implantable cardiac treatment device comprising:

microprocessor means for determining one of a plurality of cardiac treatment therapies;

cardiac sensing means for sensing the electrical activity of the heart;

external clock means for continuously generating a clock signal of a first frequency;

clock divider means for receiving as input said clock signal of said first frequency and for generating as output a plurality of clock signals at different frequencies;

a plurality of timer means for receiving as input said plurality of clock signals and producing as output time-out signals capable of being read by said microprocessor means;

auxiliary clock means for generating a clock signal of a second frequency for controlling said microprocessor means, said auxiliary clock means being capable of assuming an active state for generating said clock signal at said second frequency, and an inactive state whereby no clock signal is generated;

interrupt decision means for setting the state of said auxiliary clock means, said interrupt decision means receiving as input the output of said plurality of timer means and information related to the electrical activity of the heart as sensed by said cardiac sensing means;

clock control means for triggering said auxiliary clock means to assume one of said active or inactive states under control of said interrupt decision means and said microprocessor means; and

means to synchronize said external clock means and said auxiliary clock means so that said plurality of timer means are in a stable state when the microprocessor means reads said time-out signals.

6. The device of claim 5, wherein said clock signal of said first frequency is 32 KHz and said clock signal of said second frequency is 1 MHz.

7. An implantable microprocessor based cardiac device comprising:

microprocessor means for performing computations for determining one of a plurality of cardiac treatment therapies;

cardiac sensing means for sensing the electrical activity of the heart and producing an output signal representative thereof;

external memory means connected to said microprocessor means for storing information related to said plurality of cardiac treatment therapies;

external clock means for continuously generating a clock signal at a first frequency;

clock divider means for receiving as input said clock signal of said first frequency and for generating as output a plurality of clock signals at different frequencies;

a plurality of timer means for receiving as input said plurality of clock signals and producing as output time-out signals capable of being read by said microprocessor means;

auxiliary clock means for generating a clock signal at a second frequency for controlling said microprocessor means, said auxiliary clock means being capable of assuming an active state for generating said clock signal at said second frequency, and an inactive state whereby no clock signal is generated;

interrupt register means for receiving as input at least said output signal of said cardiac sensing means and said output from said plurality of timer means and for storing interrupt information for triggering said auxiliary clock means to assume said active state;

interrupt mask means connected to said interrupt register means for selectively inhibiting said interrupt information;

clock control means for receiving as input at least said output of said interrupt mask means and central signals from said microprocessor means for triggering said auxiliary clock means to assume one of said active or inactive states; and

means to synchronize said external clock means and said auxiliary clock means so that said plurality of timer means are in a stable state when the microprocessor means reads said time-out signals.

8. The device of claim 7, wherein said clock signal of said first frequency is 32 KHz and said clock signal of said second frequency is 1 MHz.

9. An implantable microprocessor based cardiac device comprising:

cardiac sensing means for sensing the electrical activity of the heart and producing output signals representative thereof;

cardiac treatment means for delivering a plurality of cardiac treatments to the heart in the form of electrical stimulation signals;

microprocessor means for determining one of said plurality of cardiac treatments and controlling said cardiac treatment means accordingly;

external clock means for continuously generating a clock signal of a first frequency;

clock divider means for receiving as input said clock signal of said first frequency and for generating as output a plurality of clock signals at different frequencies;

a plurality of timer means for receiving as input said plurality of clock signals and producing as output time-out signals capable of being read by said microprocessor means;

auxiliary clock means for generating a clock signal of a second frequency for controlling said microprocessor means, said auxiliary clock means being capable of assuming an active state for generating said clock signal at said second frequency, and an inactive state whereby no clock signal is generated;

interrupt decision means for setting the state of said auxiliary clock means, said interrupt decision means receiving as input the output of said plurality of timer means and information related to the electrical activity of the heart as sensed by said cardiac sensing means;

clock control means for triggering said auxiliary clock means to assume one of said active or inactive states under control of said interrupt decision means and said microprocessor means; and

means to synchronize said external clock means and said auxiliary clock means so that said plurality of timer means are in a stable state when the microprocessor means read said time-out signals.

10. The device of claim 9, wherein said clock signal of said first frequency is 32 KHz and said clock signal of said second frequency is 1 MHz.

11. An implantable microprocessor based cardiac device comprising:

cardiac sensing means for sensing the electrical activity of the heart and producing output signals representative thereof;

cardiac treatment means for delivering a plurality of cardiac treatments to the heart in the form of electrical stimulation signals;

microprocessor means for determining one of said plurality of cardiac treatments and controlling said cardiac treatment means accordingly;

external memory means connected to said microprocessor means for storing information related to said plurality of cardiac treatment therapies;

external clock means for continuously generating a clock signal at a first frequency;

clock divider means for receiving as input said clock signal of said first frequency and for generating as output a plurality of clock signals at different frequencies;

a plurality of timer means for receiving as input said plurality of clock signals and producing as output time-out signals capable of being read by said microprocessor means;

auxiliary clock means for generating a clock signal at a second frequency for controlling said microprocessor means, said auxiliary clock means being capable of assuming an active state for generating said clock signal at said second frequency, and an inactive state whereby no clock signal is generated;

interrupt register means for receiving as input at least said output signal of said cardiac sensing means and said output from said plurality of timer means and for storing interrupt information for triggering said auxiliary clock means to assume said active state;

interrupt mask means connected to said interrupt register means for selectively inhibiting said interrupt information;

clock control means for receiving as input at least said output of said interrupt mask means and central signals from said microprocessor means for triggering said auxiliary clock means to assume one of said active or inactive states; and

means to synchronize said external clock means and said auxiliary clock means so that said plurality of timer means are in a stable state when the microprocessor means reads said time-out signals.

12. The device of claim 11, wherein said clock signal of said first frequency is 32 KHz and said clock signal of said second frequency is 1 MHz.

13. An implantable microprocessor based cardiac device comprising:

microprocessing means generating control signals including an address strobe signal, a data strobe signal, and a stop clock signal;

external clock means for continuously generating a clock signal of a first frequency;

clock divider means for generating a control clock signal of a predetermined frequency different from said first frequency of said clock signal;

auxiliary clock means for generating a clock signal of a second frequency for controlling said microprocessor means when said microprocessor means performs complex computations, said auxiliary clock means being capable of assuming an active state for generating said clock signal of said second frequency and an inactive state during which no clock signal is generated;

interrupt decision means for setting the state of said auxiliary clock means and generating a start clock signal upon determining to set the auxiliary clock to an active state; and

clock control means for triggering said auxiliary clock means to assume one of said active or inactive states under control of said interrupt decision means and said microprocessor means, said clock control means comprising;

a NAND gate circuit receiving as input said stop clock signal and said data strobe signal;

a first NOR gate receiving as input said start clock signal and a master clear signal indicative of system power up of the cardiac device;

a second NOR gate receiving as input said master clear signal and said control clock signal of a predetermined frequency;

a control gate having first and second inputs and an output connected to said auxiliary clock means for maintaining said auxiliary clock means in an inactive state so long as a signal on either of said first and second inputs is high and otherwise causing said auxiliary clock to be in said active state;

first, second and third D-type flip-flops each having a clock input, a data input, a et input, a reset input, and an output;

said first D-type flip-flop receiving on its clock input an output of said NAND gate, receiving on its reset input an inverted output of said first NOR gate, the data input of said first D-type flip-flop being inverted and connected to said set input of said first D-type flip-flop, the output of said first D-type flip-flop being connected to the first input of said control gate;

said second D-type flip-flop receiving on its clock input an inversion of said address strobe signal, receiving on its reset input the inversion of the output of said second NOR gate, the data input of said second D-type flip-flop being inverted and connected to the set input of said second D-type flip-flop, the output of said second D-type flip-flop being connected to the data input of said third D-type flip-flop; and

said third D-type flip-flop receiving on its clock input an inversion of said address strobe, receiving on its reset input the inversion of the output on said second NOR gate, the output of said third D-type flip-flop being connected to said second input of said control gate.

14. The device of claim 13, wherein said first frequency generated by said external clock means is substantially lower than the second frequency generated by said auxiliary clock means.

15. A microprocessor based implantable cardiac treatment device comprising:

cardiac sensing means for sensing the electrical activity of the heart;

microprocessor means for determining one of a plurality of cardiac treatment therapies in response to the sensed electrical activity of the heart and generating control signals including an address strobe signal, a data strobe signal, and a stop clock signal;

external clock means for continuously generating a clock signal of a first frequency;

clock divider means for receiving as input said clock signal of said first frequency and for generating as output a plurality of clock signals at different frequencies including a control clock signal at a predetermined frequency;

a plurality of timer means for receiving as input said plurality of clock signals and producing as output a time-out signal;

auxiliary clock means for generating a clock signal of a second frequency for controlling said microprocessor means when said microprocessor means performs computations, said auxiliary clock means being capable of assuming an active state for generating said clock signal at said second frequency and an inactive state during which no clock signal is generated;

interrupt decision means for setting the state of said auxiliary clock means, said interrupt decision means receiving as input the output of said plurality of timer means and information related to the electrical activity of the heart as sensed by said cardiac sensing means and generating a start clock signal upon determining to activate said auxiliary clock means; and

clock control means for triggering said auxiliary clock means to assume one of said active or inactive states under control of said interrupt decision means and said microprocessor means, said clock control means comprising;

a NAND gate circuit receiving as input said stop clock signal and said data strobe signal;

a first NOR gate receiving as input said start clock signal and a master clear signal indicative of system power up of the cardiac device;

a second NOR gate receiving as input said master clear signal and said control clock signal of a predetermined frequency;

a control gate having first and second inputs and an output connected to said auxiliary clock means for maintaining said auxiliary clock means in an inactive state so long as a signal on either of said first and second inputs is high and otherwise causing said auxiliary clock to be in said active state;

first, second and third D-type flip-flops each having a clock input, a data input, a set input, a reset input, and an output;

said first D-type flip-flop receiving on its clock input an output of said NAND gate, receiving on its reset input an inverted output of said first NOR gate, the data input of said first D-type flip-flop being inverted and connected to said set input of said first D-type flip-flop, the output of said first D-type flip-flop being connected to the first input of said control gate;

said second D-type flip-flop receiving on its clock input an inversion of said address strobe signal, receiving on its reset input the inversion of the output of said second NOR gate, the data input of said second D-type flip-flop being inverted and connected to the set input of said second D-type flip-flop, the output of said second D-type flip-flop being connected to the data input of said third D-type flip-flop; and

said third D-type flip-flop receiving on its clock input an inversion of said address strobe, receiving on its reset input the inversion of the output on said second NOR gate, the output of said third D-type flip-flop being connected to said second input of said control gate.

16. The device of claim 15, wherein said first frequency generated by said external clock means is substantially slower than the second frequency generated by said auxiliary clock means.