Power MOSFET transistor circuit

• US 5,023,692 A
• Filed: 12/07/1989
• Issued: 06/11/1991
• Est. Priority Date: 12/07/1989
• Status: Expired due to Term

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation), Semiconductor Patents Incorporated
• Original Assignee: Harris Semiconductor Patents, Inc.
• Inventors: Jones, Frederich P., Neilson, John M. S., Wheatley, Carl F. Jr., Wodarczyk, Paul J.
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): FAHMY, WAEL M
• Application Number:
  US07/447,330
• Time in Patent Office: 551 Days
• Field of Search: 357/23.4, 357/43, 357/59 F, 357/46
• US Class Current: 257/370
• CPC Class Codes: H01L 27/0251 for MOS devices

Abstract

The present invention relates to a power MOS transistor having a current limiting circuit incorporated in the same substrate as the transistor. The power MOS transistor includes a drain region extending through the substrate between opposed first and second surfaces, a plurality of body regions in the substrate at the first surface, a separate source region in the substrate at the first surface within each body region and a channel extending across each body region between its junction with its respective source region and its junction with the drain region. A conductive gate is over and insulated from the first surface and extends over the channel regions. A first conductive electrode extends over and is insulated from the gate and contacts a first portion of the source regions. A second conductive electrode extends over and is insulated from the gate and contacts a second portion of the source regions. The second portion contains a smaller number of the source regions than the first portion. The current limiting circuit includes a bipolar transistor formed in a well region in the substrate, a zener diode formed in a second well region in the substrate and two resistors formed over and insulated from the first surface. The current limiting circuit is connected between the second portion of the source regions and the gate so as to reduce the power through the circuit.

Claims

1. A power MOS transistor comprising

a substrate of a semiconductor material of one conductivity type having first and second opposed surfaces;

a drain region extending through said substrate between said surfaces;

a plurality of spaced body regions of the opposite conductivity type in said substrate at said first surface, each of said body regions forming a body/drain junction with the drain region;

a separate source region of the one conductivity type in said substrate at the first surface and within each body region, each of said source regions forming a source/body junction with its respective body region which is spaced from the body/drain junction of its respective body region to form a channel region therebetween along the first surface, each of the source regions and its respective body region forming a source/body cell;

a conductive gate over and insulated from said first surface and extending across the channel regions;

a first conductive electrode over and insulated from said gate and contacting a first portion of the source/body cells;

a second conductive electrode over and insulated from said gate and contacting a second portion of the source/body cells, the number of source/body cells in the second portion being smaller than the number in the first portion;

a bipolar transistor in said substrate at said first surface having a collector region, an emitter region and a base region;

a diode in the substrate at said first surface, said diode having first and second regions of opposite conductivity type; and

first and second resistors over and insulated from said first surface;

one end of the first resistor being connected to one side of the diode and the other end of the first resistor being connected to the collector of the bipolar transistor and the gate;

one end of the second resistor being connected to the base of the bipolar transistor and the second electrode; and

the emitter of the bipolar transistor being connected to the other side of the diode and to the first electrode.

2. A power MOS transistor in accordance with claim 1 in which the bipolar transistor comprises a well region of the opposite conductivity type in the substrate at the first surface serving as the base, at least one region of the one conductivity type in the substrate at the first surface within the well region serving as the collector, and at least one region of the one conductivity type in the substrate at said surface within the well region serving as the emitter.

3. A power MOS transistor in accordance with claim 2 in which the bipolar transistor includes a plurality of the emitter regions in spaced relation in the base region, and a separate collector region surrounding each of the emitter regions.

4. A power MOS transistor in accordance with claim 2 in which the diode comprises a well region of the opposite conductivity type in the substrate at said first surface, and a region of the one conductivity type in the substrate at said first surface within said well region.

5. A power MOS transistor in accordance with claim 4 in which each of the resistors comprises a strip of a partially conductive material over and insulated from said first surface.

6. A power MOS transistor in accordance with claim 5 in which the strip forming the second resistor is over the well region containing the bipolar transistor.

7. A power MOS transistor in accordance with claim 6 in which the second resistor comprises a plurality of spaced parallel strips of the partially conductive material.

8. A power MOS transistor in accordance with claim 6 in which the strip forming the first resistor extends between the two well regions.