High-speed press control system

• US 5,023,770 A
• Filed: 04/11/1988
• Issued: 06/11/1991
• Est. Priority Date: 04/11/1988
• Status: Expired due to Term

• Current Assignee: Square D Company (Schneider Electric SE)
• Original Assignee: Square D Company (Schneider Electric SE)
• Inventors: Siverling, Erich H.
• Primary Examiner(s): MacDonald, Allen R.
• Application Number:
  US07/179,743
• Time in Patent Office: 1,156 Days
• Field of Search: 364/140, 364/141, 364/146, 364/147, 364/136
• US Class Current: 700/11
• CPC Class Codes: G05B 19/054 Input/output
• CPC Class Codes: G05B 2219/1151 Fast scanning of I-O to put I-O status in image table
• CPC Class Codes: G05B 2219/1159 Image table, memory
• CPC Class Codes: G05B 2219/15102 Programmer simulates, behaves like a programming drum

Abstract

A high-speed press control system including a control processor and an associated scan processor for executing a press algorithm providing timed interrupts and consisting of identical programmable sub-algorithms to control output and input registers. The high-speed press control system has the capability of monitoring and reacting to press position every 2.5 ms.

Claims

1. A programmable logic controller (PLC) for controlling a high-speed machine operating in cycle-type modes, the machine having a plurality of components having at least two status states, the PLC comprising:

an executive memory,

an image memory including an input image table and an output image table,

a machine control algorithm,

an internal clock for generating repetitive timed interrupts,

a control processor for coordinating operation of the system in accordance with instructions contained in said executive memory, including updating of said image memory;

a communication bus adapted for communicating with the machine; and

a scan processor having its own executive memory, said scan processor for reading said input image table, executing said machine control algorithm and updating said output image table in response to said repetitive timed interrupts.

2. The PLC of claim 1, wherein the algorithm resides in said executive memory of said scan processor.

3. The PLC of claim 1, wherein the algorithm is executed in response to said repetitive timed interrupts by said scan processor.

4. The PLC of claim 1, wherein the algorithm comprises a multiple function block software.

5. The PLC of claim 1, wherein the algorithm comprises multiple executions of substantially the same sub-algorithm.

6. The PLC of claim 1, wherein the control processor provides control commands to said scan processor and receives inputs from said scan processor for communicating with the machine.

7. The PLC of claim 1, further including a user memory for containing the user program, and said user memory connecting directly to said scan processor, said user program controlling the operation and sequence of said scan processor.

8. The PLC of claim 1, wherein the repetitive timed interrupt is a multiple of 2.5 milliseconds and wherein the image memory is updated every scan cycle.