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Apparatus for skipping arithmetic calculations involving leading zeros

  • US 5,023,826 A
  • Filed: 01/11/1990
  • Issued: 06/11/1991
  • Est. Priority Date: 01/11/1990
  • Status: Expired due to Fees
First Claim
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1. In a digital computer having an ALU for performing arithmetic computation upon pairs of operands, a memory means connected to the ALU and organized as addressable words for storing operands, where an operand occupies a number of contiguous words, and fetching means for presenting the operands for storage in the memory means a word at a time, least significant word first,apparatus for bypassing computation of those word positions of operands which contain no significant digits in either operand of the pair, comprising:

  • OR gate means connected to the fetching means for determining whether an operand word contains non-zero digits;

    first register means operatively connected to the OR gatemeans for storing the number of words containing significant digits in a first operand of the pair;

    second register means operatively connected to the OR gatemeans for storing the number of words containing significant digits in the second operand of the pair;

    comparator means for determining an index number equal to the greater of the first register means contents and the second register means contents; and

    means for terminating computation after one more than said index number of word positions have been computed.

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