Apparatus for skipping arithmetic calculations involving leading zeros
First Claim
1. In a digital computer having an ALU for performing arithmetic computation upon pairs of operands, a memory means connected to the ALU and organized as addressable words for storing operands, where an operand occupies a number of contiguous words, and fetching means for presenting the operands for storage in the memory means a word at a time, least significant word first,apparatus for bypassing computation of those word positions of operands which contain no significant digits in either operand of the pair, comprising:
- OR gate means connected to the fetching means for determining whether an operand word contains non-zero digits;
first register means operatively connected to the OR gatemeans for storing the number of words containing significant digits in a first operand of the pair;
second register means operatively connected to the OR gatemeans for storing the number of words containing significant digits in the second operand of the pair;
comparator means for determining an index number equal to the greater of the first register means contents and the second register means contents; and
means for terminating computation after one more than said index number of word positions have been computed.
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Abstract
In a digital computer system which may perform arithmetic computations on multi-word variable-length operands, and in which computation is performed right to left (least significant digit first), apparatus detects when all word positions containing significant digits have been computed and terminates computation after computing one additional word position to allow any carry to propagate. Additional apparatus forces zeros for those word positions of an operand that do not contain significant digits, for they may be non-existent positions.
102 Citations
6 Claims
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1. In a digital computer having an ALU for performing arithmetic computation upon pairs of operands, a memory means connected to the ALU and organized as addressable words for storing operands, where an operand occupies a number of contiguous words, and fetching means for presenting the operands for storage in the memory means a word at a time, least significant word first,
apparatus for bypassing computation of those word positions of operands which contain no significant digits in either operand of the pair, comprising: -
OR gate means connected to the fetching means for determining whether an operand word contains non-zero digits; first register means operatively connected to the OR gate means for storing the number of words containing significant digits in a first operand of the pair; second register means operatively connected to the OR gate means for storing the number of words containing significant digits in the second operand of the pair; comparator means for determining an index number equal to the greater of the first register means contents and the second register means contents; and means for terminating computation after one more than said index number of word positions have been computed. - View Dependent Claims (2)
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3. In a digital computer having an ALU for performing arithmetic computation upon pairs of operands, a memory means connected to the ALU and organized as addressable words for storing operands, where an operand occupies a number of contiguous words, and fetching means for presenting the operands for storage in the memory means a word at a time, least significant word first,
a apparatus for bypassing computation of those word positions of operands which contain no significant digits in either operand of the pair, comprising: -
OR gate means connected to the fetching means for determining whether an operand word contains non-zero digits; first register means operatively connected to the OR gate means for storing the number of words containing significant digits in a first operand of the pair; second register means operatively connected to the OR gate means for storing the number of words containing significant digits in the second operand of the pair; and first and second forcing means responsive to the first and second register means respectively for forcing the first and second operand word positions, respectively, to zero in word positions in which the first or second operand, respectively, does not contain significant digits. - View Dependent Claims (4)
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5. In a digital computer having an ALU for performing arithmetic computation upon pairs of operands, a memory means connected to the ALU and organized as addressable words for storing operands, where an operand occupies a number of contiguous words, and fetching means for presenting the operands for storage in the memory means a word at a time, least significant word first,
apparatus for bypassing computation of those word positions of operands which contain no significant digits in either operand of the pair, comprising: -
OR gate means connected to the fetching means for determining whether an operand word contains non-zero digits; first register means operatively connected to the OR gate means for storing the number of words containing significant digits in a first operand of the pair; second register means operatively connected to the OR gate means for storing the number of words containing significant digits in the second operand of the pair; comparator means for determining an index number equal to the greater of the first register means contents and the second register means contents; and means for terminating computation after one more than said index number of word positions have been computed; and first and second forcing means responsive to the first and second register means respectively for forcing the first and second operand word positions, respectively, to zero in word positions in which the first or second operand, respectively, does not contain significant digits. - View Dependent Claims (6)
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Specification