Semiconductor memory system for use in logic LSI's

• US 5,023,835 A
• Filed: 05/10/1989
• Issued: 06/11/1991
• Est. Priority Date: 02/19/1986
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Ogiue, Katsumi, Akimoto, Kazuhiro, Uchiyama, Takeo
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/351,044
• Time in Patent Office: 762 Days
• Field of Search: 365/189.01, 365/189.05, 365/230.08, 365/230.03, 365/155, 365/156, 365/230.06, 365/189.08, 365/174, 307/449, 307/455, 307/465, 307/494
• US Class Current: 365/155
• CPC Class Codes: G11C 11/415 Address circuits
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

A semiconductor memory system includes a memory section formed on a semiconductor substrate and having decode means for decoding an address signal, and a logic section formed on the semiconductor substrate and having address signal forming means for forming an address signal for the memory section and address signal delivering means for delivering the address signal for the memory section to the decode means. The address signal delivered from the address signal delivering means is defined by complementary signals.

Claims

1. A memory system formed on a single semiconductor substrate comprising:

a memory section having decode means for decoding a pair of complementary address signals;

a latch circuit means having a bipolar transistor for delivering said pair of complementary address signals to said decode means; and

first and second lines coupled between said decode means of said memory section and said latch circuit for transmitting said pair of complementary address signals from said latch circuit to said decode means of said memory section,

wherein said latch circuit receives a plurality of address signals Al-AN, and wherein said latch circuit includes a plurality of unit latch circuits, each of which unit latch circuits respectively receives an individual one address signal Al-AN, and each of which unit latch circuits includes means for converting the received one of said address signals into a pair of said complementary address signals, and

wherein each of said unit latch circuits is comprised of a first differential transistor pair having a first bipolar transistor and a second bipolar transistor, wherein a base of the first bipolar transistor is coupled to receive one of said address signals Al-AN, and wherein a base of the second bipolar transistor receives a predetermined reference voltage, wherein each of said unit latch circuits further comprises a second differential transistor pair having a third bipolar transistor and a fourth bipolar transistor, each having bases coupled to receive feedback signals from outputs of said unit latch circuits, and wherein each of said unit latch circuits further comprises means for selectively operating either said first differential pair or said second differential pair.

2. A memory system according to claim 1, wherein said selective operating means comprises a third differential transistor pair coupled to said first and second differential circuits, wherein said third differential transistor pair comprises fifth and sixth bipolar transistors having emitters thereof coupled in common to a constant current source.

3. A memory system formed on a single semiconductor substrate comprising:

first and second memory blocks each having output means for outputting a pair of complementary signals read out from a memory cell in said memory section;

a logic section coupled to receive pairs of complementary signals from said first and second memory blocks for carrying out a logical processing operation in response to said pairs of complementary signals; and

a plurality of pairs of first and second lines each respectively coupled between said first and second memory blocks and said logic section for transmitting said pairs of complementary signals,

wherein said output means for each of said first and second memory blocks includes a first emitter follower transistor, the base of which is coupled to said memory cell and the emitter of which is coupled to said first line, and a second emitter follower transistor, the base of which is coupled to said memory cell and the emitter of which is coupled to said second line, and

wherein said logic section includes a first transistor, the base of which is coupled to said first line, the collector of which is coupled to a first output terminal and the emitter of which is coupled to a current source, and a second transistor, the base of which is coupled to said second line, the collector of which is coupled to a second output terminal and the emitter of which is coupled to said emitter of said first transistor.

4. A memory system formed on a single semiconductor substrate comprising:

first and second memory blocks each having output means for outputting a pair of complementary signals read out from a memory cell in said memory section;

a logic section coupled to receive pairs of complementary signals from said first and second memory blocks for carrying out a logical processing operation in response to said pairs of complementary signals; and

a plurality of pairs of first and second lines each respectively coupled between said first and second memory blocks and said logic section for transmitting said pairs of complementary signals,

wherein said logic section includes a selecting circuit having a first bipolar transistor having a base coupled to receive one signal of a pair of complementary signals and a second bipolar transistor having a base to receive the other signal of said pair of complementary signals, wherein said first and second bipolar transistors are coupled to one another to form a differential circuit having their respective emitters coupled to one another.

5. A memory system according to claim 4, wherein said logic section further includes a latch circuit coupled to receive outputs of said selecting circuit.

6. A memory system formed on a single semiconductor substrate comprising:

first and second memory blocks each having output means for outputting a pair of complementary signals read out from a memory cell in said memory section;

a logic section coupled to receive pairs of complementary signals from said first and second memory blocks for carrying out a logical processing operation in response to said pairs of complementary signals; and

a plurality of pairs of first and second lines each respectively coupled between said first and second memory blocks and said logic section for transmitting said pairs of complementary signals,

wherein said logic section includes a selecting circuit having a first bipolar transistor having a base coupled to receive one signal of a first pair of complementary signals from said first memory block, a second bipolar transistor having a base coupled to receive the other signal of said first pair of complementary signals from said first memory block, a third bipolar transistor having a base coupled to receive one signal of a second pair of complementary signals from said second memory block and a fourth bipolar transistor having a base coupled to receive the other signal of said second pair of complementary signals from said second memory block, wherein said first and second bipolar transistors are coupled to form a first differential circuit having their emitters coupled to one another, and wherein said third and fourth bipolar transistors are coupled to form a second differential circuit having their emitters coupled to one another.

7. A memory system according to claim 6, further comprising a fifth bipolar transistor coupled to the emitters of said first and second bipolar transistors and a sixth bipolar transistor coupled to the emitters of said third and fourth bipolar transistors, wherein said fifth and sixth bipolar transistors form a third differential circuit having their emitters coupled to one another and to a constant current source, and wherein said fifth and sixth bipolar transistors have their bases respectively coupled to receive complementary clock signals.

8. A memory system according to claim 7, wherein the collectors of said first and third bipolar transistors are coupled to provide a first output signal of said selecting circuit, and wherein the collectors of said second and fourth bipolar transistors are coupled to provide a second output signal of said selecting circuit.

9. A memory system according to claim 8, wherein said logic section further includes a latch circuit coupled to receive said first and second output signals of said selecting circuit.

10. A memory system according to claim 9, wherein said selecting means further includes a first emitter follower circuit having a base coupled to the collectors of the first and third bipolar transistors and an emitter coupled to said latch circuit, and a second emitter follower circuit having a base coupled to the collectors of the second and fourth bipolar transistors and an emitter coupled to said latch circuit, such that the first output signal of the selecting means is provided at the emitter of the first emitter follower circuit and the second output signal of the selecting means is provided at the emitter of the second emitter follower circuit.

11. A memory system formed on a single semiconductor substrate comprising:

a memory section having decode means for decoding a pair of complementary address signals and output means for outputting a pair of complementary signals read out from a memory cell in said memory section;

a latch circuit having means for delivering said pair of complementary address signals to said decode means;

a logic section for carrying out a logical processing operation in response to said pair of complementary signals;

first and second lines coupled between said decode means of said memory section and said latch circuit for transmitting said pair of complementary address signals to said decode means; and

third and fourth lines coupled between said output means of said memory section and said logic section for transmitting said pair of complementary signals to a second logic section,

wherein said latch circuit receives a plurality of address signals Al-AN, and wherein said latch circuit includes a plurality of unit latch circuits, each of which unit latch circuits respectively receives an individual one address signal Al-AN, and each of which unit latch circuits includes means for converting the received one of said address signals into a pair of said complementary address signals, and

wherein each of said unit latch circuits is comprised of a first differential transistor pair having a first bipolar transistor and a second bipolar transistor, wherein a base of the first bipolar transistor is coupled to receive one of said address signals Al-AN, and wherein a base of the second bipolar transistor receives a predetermined reference voltage, wherein each of said unit latch circuits further comprises a second differential transistor pair having a third bipolar transistor and a fourth bipolar transistor, each having bases coupled to receive feedback signals from outputs of said unit latch circuits, and wherein each of said unit latch circuits further comprises means for selectively operating either said first differential pair or said second differential pair.

12. A memory system according to claim 11, wherein said selective operating means comprises a third differential circuit coupled to said first and second differential circuits, wherein said third differential circuit comprises fifth and sixth bipolar transistors having emitters thereof coupled in common to a constant current source.

13. A memory system formed on a single semiconductor substrate comprising:

a first random access memory having a decode section;

a second random access memory having a decode section; and

a first logic circuit coupled to said first and second random access memories, wherein said first logic circuit comprises;

a read address increment circuit having means for producing a read address signal in response to a first external signal received by said read address increment circuit;

a write address increment circuit having means for producing a write address signal in response to a second external signal received by said write address increment circuit;

a first latch circuit;

a second latch circuit; and

selecting means coupled to receive said read address signal and said write address signal from said read address increment circuit and said write address increment circuit, wherein said selecting means includes means for providing an output to said first and second latch circuits,

wherein said first and second latch circuits include means to deliver pairs of complementary address signals to said first and second random access memories in accordance with said read address signal and said write address signal, wherein said selecting means includes means for providing said read address signal to one of said first and second random access memories and means for providing said write address signal to the other of said first and second random access memories,

wherein said first and second random access memories each have an output means for outputting a pair of data complementary signals read out from a memory cell of the first and second random access memories, respectively, and wherein said memory system further comprises a second logic circuit coupled to the output means of the first and second random access memories and including means for carrying out a logical processing operation in response to a received pair of data complementary signals from one of the first and second random access memories.

14. A memory system according to claim 13, wherein said second logic circuit includes a selecting means for selecting either a pair of complementary data signals from the output means of the first random access memory or a pair of complementary data signals from the output means of the second random access memory, and wherein said second logic circuit further includes a third latch circuit coupled to an output of the selecting means for latching the pair of complementary data signals selected by the selecting means.

15. A memory system according to claim 14, further comprising an output buffer coupled to receive an output from said third latch circuit.

16. A memory system according to claim 13, wherein said second logic circuit includes a selecting circuit having a first bipolar transistor having a base coupled to receive one signal of a pair of complementary signals and a second bipolar transistor having a base to receive the other signal of said pair of complementary signals, wherein said first and second bipolar transistors are coupled to one another to form a differential circuit having their respective emitters coupled to one another.

17. A memory system according to claim 13, wherein said second logic circuit includes a selecting circuit having a first bipolar transistor having a base coupled to receive one signal of a first pair of complementary signals from said first memory block, a second bipolar transistor having a base coupled to receive the other signal of said first pair of complementary signals from said first memory block, a third bipolar transistor having a base coupled to receive one signal of a second pair of complementary signals from said second memory block and a fourth bipolar transistor having a base coupled to receive the other signal of said second pair of complementary signals from said second memory block, wherein said first and second bipolar transistors are coupled to form a first differential circuit having their emitters coupled to one another, and wherein said third and fourth bipolar transistors are coupled to form a second differential circuit having their emitters coupled to one another.

18. A memory system according to claim 17, further comprising a fifth bipolar transistor coupled to the emitters of said first and second bipolar transistors and a sixth bipolar transistor coupled to the emitters of said third and fourth bipolar transistors, wherein said fifth and sixth bipolar transistors form a third differential circuit having their emitters coupled to one another and to a constant current source, and wherein said fifth and sixth bipolar transistors have their bases respectively coupled to receive complementary clock signals.