Random access memory device with integral logic capability

• US 5,023,838 A
• Filed: 12/02/1988
• Issued: 06/11/1991
• Est. Priority Date: 12/02/1988
• Status: Expired due to Term

• Current Assignee: Magnachip Semiconductor Limited (Magnachip Semiconductor)
• Original Assignee: NCR Corporation (NCR Voyix Corporation)
• Inventors: Herbert, Brian K.
• Primary Examiner(s): Bowler, Alyssa H.
• Application Number:
  US07/279,606
• Time in Patent Office: 921 Days
• Field of Search: 365/189.05, 365/189.080, 365/221, 365/239, 365/230.03, 365/445, 365/448, 365/207, 365/208, 307/465, 307/468, 307/530
• US Class Current: 365/189.08
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A random access memory (RAM) device capable of performing logic combinations of new and previously stored data in a single memory access cycle. In contrast to conventional RAM data combination sequences, which involve a succession of read-modify-write cycles, the present architecture implements logical combinations of new RAM data with old RAM data during a single access cycle. In a preferred arrangement, decoding logic combines the new data with mode select signals to generate a set of FORCE 1, FORCE 0, COMP and NOOP control signals. The control signals regulate the bit line sense amplifier and logic to allow direct interaction with the bit line data during RAM addressing. The invention is particularly useful in graphic video display systems frame buffers where rapid pattern changes are difficult to implement using moderate speed and cost RAM devices.

Claims

1. A circuit for rapidly entering logic combinations of new and previously stored data into a random access memory, comprising:

a random access memory having a row decoder for selecting an addressed row line from the array;

sense amplifier responsive to data signals from the memory array bit lines;

mode logic means for generating control signals as defined by selected logical combinations and new data signals; and

means for altering the data in the sense amplifier during the addressing of a row line from the array in response to mode logic control signals

wherein the sense amplifier and means for directly altering the data in the sense amplifier are situated between the random access memory array bit lines and a column decoder; and

wherein the means for altering the data in the sense amplifier includes;

means for producing a direct complement of the previously stored data selected during the addressing of a row line;

means for sensing the binary state of the memory array bit lines; and

means for selectively driving the binary state of the sensed memory array bit line states to a binary "0" or binary "1" as defined by the mode logic control signals.

2. The apparatus recited in claim 1, wherein the mode logic control signals for producing a direct complement of the previously stored data are based upon a logical combination of a bit line write signal, an inverted feedback of the previously stored data, and a complement control signal from the mode logic means.

3. A random access memory circuit having a sense amplifier with integrated logic, comprising:

a random access memory array having a row decoder for selecting a row of bit lines from the array;

a sense amplifier responsive to data signals from an array bit line and including a sample node selectively connectible to the bit line and to a forced state input line;

means for holding data signals from the array bit line on the sample node while driving the bit line with a complement data signal; and

mode logic means for generating control signals to define logical combinations of bit line data previously stored in the random access memory array with new data in the sense amplifier;

wherein the operation defined by the mode logic means and implemented in the sense amplifier is accomplished within a single random access memory array write cycle time interval.