Protocol and apparatus for selectively scanning a plurality of lines connected to a communication device

• US 5,023,867 A
• Filed: 01/19/1989
• Issued: 06/11/1991
• Est. Priority Date: 01/22/1988
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Spalmacin-Roma, Sylvie, Franquenouille, Jean-Paul, Dambricourt, Richard, Garcia, Christian, Badaoui, Mohamed, Granger, Yves
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Chin, Wellington
• Application Number:
  US07/299,865
• Time in Patent Office: 873 Days
• Field of Search: 370/56, 370/85.8, 370/95.2, 370/112, 370/95.1, 340/825.1, 340/825.12, 340/825.13, 340/825.54
• US Class Current: 370/434
• CPC Class Codes: G06F 12/0661 and decentralised selection
• CPC Class Codes: G06F 13/225 with priority control
• CPC Class Codes: G06F 13/385 for adaptation of a particular data processing system to different peripheral devices
• CPC Class Codes: H04L 12/40032 Details regarding a bus interface enhancer
• CPC Class Codes: H04L 12/403 with centralised control, e.g. polling
• CPC Class Codes: H04L 12/525 involving a stored program control
• CPC Class Codes: H04L 61/5038 for local use, e.g. in LAN or USB networks, or in a controller area network [CAN]

Abstract

A scanning protocol is provided for the scanning of a plurality of serial transmission lines connecting users'"'"' devices to the scanning means of a communication device, said lines being coupled to the scanning means through line interface couplers (LICs) having each a wired address (n,n'"'"', . . . ) known to the scanning means. This scanning protocol requires that for each LIC configuration, a given LICn having a wired address n be re-addressable with a logical address n'"'"' corresponding to the wired address of any other active LICn'"'"'. This is done in order to determine, for said LIC configuration, the shortest possible scanning scheme including all the active LICs. The re-addressing of a LICn of wired address n, with a logical address n'"'"', includes the steps of: resetting the LICn to be affected a logical address n'"'"'; setting the logical address n'"'"' into LICn; locking said logical address n'"'"' into said LICn, and enabling the lines (26) connected to LICn re-addressed with logical address n'"'"'.

Claims

1. A scanning protocol for scanning a plurality of serial transmission lines (26) connecting users'"'"' devices to scanning means (10, 16, 17) of a communication device, said lines being coupled to the scanning means through line interface couplers (LICs) (20) which are plugged to the scanning means at physical addresses whereby each line interface coupler LIC has a wired address corresponding to its physical address which is known to the scanning means, said protocol being characterized by the fact that, for each configuration of active line interface couplers effectively connected to active serial transmission lines each active line interface coupler LIC is re-addressable with a logical address corresponding to the wired address of any line interface coupler LIC in order to determine, for said configuration of active line interface couplers LICs, the shortest possible scanning scheme including only the active line interface couplers connected to active serial transmission lines, said scanning scheme being based upon the logical addresses.

2. A scanning protocol according to claim 1, wherein a line interface coupler LIC having a wired address n, is re-addressable with a logical address corresponding to the wired address n'"'"' of any other line interface coupler and the active line interface coupler of wired address n'"'"' is re-addressable with a logical address corresponding to the wired address n so that both line interface couplers LICs of wired address n and n'"'"' have their addresses swapped.

3. A logical addressing protocol according to claim 1, implemented in a communication device wherein each line interface coupler can be set in a disable or enable state for preventing or allowing said line interface coupler to receive and send data on the serial transmission lines connected to it, respectively, for re-addressing a line interface coupler of wired address n, with a logical address n'"'"', characterized by the fact that it includes the steps of:

setting the line interface coupler of wired address n to be assigned a logical address n'"'"', in its disable state

setting the logical address n'"'"' into line interface coupler of wired address n;

locking said logical address n'"'"' into said, and

setting the line interface coupler of wired address n re-addressed with logical address n'"'"' in its enable state.

4. A logical addressing protocol according to claim 1 or 2, implemented in a communication device wherein each line interface coupler can be set in a disable or enable state for preventing or allowing said line interface coupler to receive and send data on the serial transmission lines connected to it respectively, for swapping the addresses n and n'"'"' of two line interface couplers so that line interface coupler of wired address n be assigned n'"'"' as logical address and line interface coupler of wired address n'"'"' be assigned n as a logical address, wherein said protocol includes successively the steps of:

setting both line interface couplers of wired addresses n and n'"'"' in their disable states;

setting the logical address n'"'"' into line interface coupler of wired address n and locking said logical address n'"'"',

setting the line interface coupler of wired address n with the logical address n'"'"' previously set in its enable state;

setting the line interface coupler of wired address n'"'"' with the logical address n previously set in its enable state, so that after completion of said steps, the data traffic between the scanning means and the lines connected to line interface coupler of wired address n is transferred onto line interface coupler of wired address n'"'"', and the data traffic between the scanning means and the lines connected to line interface coupler of wired address n'"'"' is transferred onto line interface coupler of wired address n.

5. A logical addressing protocol according to claim 3 wherein said steps are performed through the exchange of control words between control registers (72, 74) located in the line interface couplers being re-addressed, and dedicated control slots (CAx, CBx) of the data flow arranged in superframes each one superframe comprising a plurality of frames with each frame comprising at least one control slot and a data slot assigned to each serial transmission line and each slot being able to transport a plurality of bits on a serial link (12) implemented between the scanning means (10, 16, 17) and the line interface couplers, the timing of said steps being provided by the bit, slot, frame and superframe counts of said serial data flow.

6. A logical addressing protocol according to claims 5 wherein, for the setting of a logical address n'"'"' into line interface coupler of wired address n, said line interface coupler decodes a first control slot CBx of a first control frame FBx in a superframe of the serial data flow, upon receipt by line interface coupler of wired address n of a LIC ADDRESS DETECT signal, said control slot CBx containing the logical address n'"'"'=b'"'"'0, b'"'"'1, b'"'"'2 to be set into line interface coupler of wired address n and a LOGICAL ADDRESS ENABLE bit (EnLA), the logical address n'"'"' being set into an address register RA (72) of line interface coupler of wired address n only if said LOGICAL ADDRESS ENABLE bit is inactive, and the logical address n'"'"' being effectively locked into line interface coupler of wired address n only upon receipt by line interface coupler of wired address n of a synchronization tag provided to line interface coupler of wired address n during a frame (F31x) succeeding frame FBx.

7. A logical addressing protocol according to claim 6, wherein the line interface coupler of wired address n is enabled with the logical address n'"'"' set during frame FBx, upon receipt by said line interface coupler of wired address n, of a second control slot CA(x+1) located in a second control frame FA(x+1) of a succeeding superframe (x+1), said second control slot CA(x+1) containing LIC enable bits E0, E1, the status of which determines the operation mode of said line interface coupler of wired address n.

8. An apparatus for the implementation of the logical addressing protocol according to claims 5 wherein said apparatus, located in each line interface coupler, includes:

counting means (40) incremented at the bit clock rate of the serial link and provided with a frame synchronization tag and a superframe synchronization tag, said counting means (40) providing a slot count, a line count and a frame count;

an address register RA (72) containing the logical address A=b0, b1, b2 affected to the LICn, and an "Enable Logical Address" bit (EnLA), said address register RA (72) being loaded, upon activation of a D1 decode, by a parallel register (58) continuously filled by a deserializer (56) providing the outbound serial data flow;

a control register RC (74) containing two "LIC Enable" bits E0 E1 provided to said register (74) by said parallel register (58) upon activation of a D2 decode;

an address selector (76) for selecting, according to the value of said EnLA bit, the physical address of the line interface coupler, provided by a wired address bus (88), or the logical address A provided by said address register RA (72);

an address comparator (70) for comparing a count derived from the serial data flow by the counting means (40), indicative of the slots assigned to the transmission lines connected to the line interface coupler, and the selected logical or wired address, said comparator generating a LIC ADDRESS DETECT time window in case of egality, for giving the line interface coupler access to the serial data flow during said time window.