Method of obtaining semiconductor chips

• US 5,024,970 A
• Filed: 12/05/1989
• Issued: 06/18/1991
• Est. Priority Date: 06/27/1989
• Status: Expired due to Fees

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Mori, Masataka
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): DANG, TRUNG Q
• Application Number:
  US07/446,125
• Time in Patent Office: 560 Days
• Field of Search: 437/226, 437/227, 437/228, 148/DIG. 28
• US Class Current: 438/462
• CPC Class Codes: H01L 21/3043 Making grooves, e.g. cutting
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: Y10S 148/028 Dicing

Abstract

An insulating strip layer is provided in the middle portion of an isolating zone which isolates electronic element regions from each other. A platinum layer is formed and sintered, whereby platinum silicide layers are obtained between the insulating strip layer and the electronic element regions. A silicon nitride film is formed and etched by plasma. The plasma etches the silicon nitride film and selectively etches the wafer through the gaps between the platinum silicide layers and layers adjacent thereto whereby grooves are obtained in the isolating zone. A crack which may be caused in the cutting or dicing process is stopped at the grooves.

Claims

1. A method of obtaining semiconductor chips by cutting a semiconductor wafer in which a plurality of electronic element regions are provided, comprising the steps of:

(a) forming first and second electronic element regions on a major surface of said semiconductor wafer such that said first and second electronic element regions are isolated from each other across an isolating zone on said major surface, wherein said isolating zone extends in a first direction perpendicular to an alignment direction of said first and second electronic element regions;

(b) forming N grooves in said isolating zone parallel to said first direction, wherein (N-1) intergroove spaces intervene between said N grooves and N is an integer larger than one; and

(c) cutting said semiconductor wafer along a cutting line which is set on one of said (N-1) intergroove spaces and extends in said first direction to thereby obtain semiconductor chips each having an electronic element region;

wherein step (a) comprises the steps of;

(a-1) forming first and second active regions in said major surface, each of said first and second active regions having at least one electronic element; and

(a-2) providing first and second insulating layers which cover said first and second active regions, respectively, to thereby obtain said first and second electronic element regions;

step (b) comprises the steps of;

(b-1) forming an insulating strip layer which extends in said first direction is a middle portion of said isolating zone, whereby a first gap is defined between said first insulating layer and said insulating strip layer, and a second gap is defined between said second insulating layer and said insulating strip layer; and

(b-2) forming first and second grooves in said isolating zone such that said first groove is aligned with a first side wall of said insulating strip layer facing said first insulating layer across said first gap, and said second groove is aligned with a second side wall of said insulating strip layer facing said second insulating layer across said second gap, and

step (c) comprises the steps of;

(c-1) setting said cutting line on said insulating strip layer; and

(C-2) cutting said semiconductor wafer at said cutting line with a mechanical dicing tool.

2. A method of claim 1, wherein

step (b) further comprises the step of:

(b-3) forming third and fourth grooves in said isolating zone such that said third groove is aligned with a side wall of said first insulating layer facing said first side wall of said insulating strip layer across said first gap, and said fourth groove is aligned with a side wall of said second insulating layer facing said second side wall of said insulating strip layer across said second gap.

3. A method of claim 2, wherein steps (b-2) and (b-3) in combination comprise the steps of:

(b-4) forming first and second etching-resistant layers on first and second areas of said isolating zone, respectively, in which said first area is located between said first insulating layer and said insulating strip layer on said major surface, and said second area is located between said second insulating layer and said insulating strip layer on said major surface,

providing a first gap space between said insulating strip layer and said first etching-resistant layer,

providing a second gap space between said insulating strip layer and said second etching-resistant layer,

providing a third gap space between said first insulating layer and said first etching-resistant layer,

providing a fourth gap space between said second insulating layer and second etching-resistant layer, and

(b-5) selectively etching said semiconductor wafer through said first to fourth gap spaces to thereby obtain said first to fourth grooves, respectively.

4. A method claim 3, wherein

step (b-5) comprises the steps of:

forming a third insulating layer covering respective regions on said major surface;

forming first and second resist films on first and second portions of said third insulating layer which are located on said first and second insulating layers, respectively;

applying a plasma to respective regions on said major surface so that portions of said third insulating layer not covered with said first and second resist films are etched away and then said first to fourth grooves are formed through selective etching of said semiconductor wafer by said plasma passing through said first to fourth gap spaces, respectively; and

removing said first and second resist films from said semiconductor wafer.

5. A method of claim 4, wherein

step (b-4) comprises the steps of:

forming a metal layer covering respective regions on said major surface;

heating said semiconductor wafer together with said metal layer to thereby convert first and second portions of said metal layer contacting said semiconductor wafer in said first and second gaps into first and second metal-semiconductor composite layers serving a said first and second etching-resistant layers, respectively; and

removing respective portions of said metal layer other than said first and second portions.

6. A method of claim 5, comprising

each width of said first to fourth grooves being larger than each width of said first to fourth gap spaces in said first direction, and

said first to fourth grooves being first to fourth cavities having openings communicating said first to fourth gap spaces, respectively.

7. A method of claim 6, wherein

a half of each width of said first to fourth grooves being smaller than a half of width of said insulating strip layer in said alignment direction.

8. A method of claim 7, comprising

etching each depth of said first to fourth grooves to about one micron.

9. A method of claim 8, comprising:

said semiconductor wafer being a silicon wafer,

said first and second insulating layers and said insulating strip layer being made of silicon oxide,

said third insulating layer being made of silicon nitride, and

a material of said metal layer being one of platinum, tungsten and molybdenum.