Apparatus for decoding frames from a data link

• US 5,025,458 A
• Filed: 10/30/1989
• Issued: 06/18/1991
• Est. Priority Date: 10/30/1989
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Kalos, Matthew J., Huang, Catherine C., Flanagan, John R., Gregg, Thomas A., Casper, Daniel F.
• Primary Examiner(s): Safourek, Benedict V.
• Assistant Examiner(s): Bocure, Tesfaldet
• Application Number:
  US07/429,257
• Time in Patent Office: 596 Days
• Field of Search: 375/114, 375/116, 370/105.1, 370/105.4, 364/715.11, 371/47.1
• US Class Current: 375/365
• CPC Class Codes: H04J 3/0608 Detectors therefor, e.g. correlators, state machines
• CPC Class Codes: H04L 2007/045 Fill bit or bits, idle words
• CPC Class Codes: H04L 7/0066 detection of error based on transmission code rule
• CPC Class Codes: H04L 7/048 using the properties of error detecting or error correcting codes, e.g. parity as synchronisation signal

Abstract

An apparatus for decoding frames from a data link including a multiple entry expect/mask buffer an input for receiving multiple character frames, a comparator for comparing characters received from the data link with expected characters in the expect/mask buffer as masked by a mask also in the expect/mask buffer, a multiple entry header buffer for storing characters of frames received by the input, and a multiple entry compare buffer for storing in an entry the results of the comparison of the characters stored in the corresponding entry in the header buffer to expected characters as masked by the mask in a corresponding entry of the expect/mask buffer. Storage into the header buffer and the compare buffer is stopped by terminating events which are detected by a state machine. A data frame recognition circuit is provided which detects a variety of data frames from among the frames transmitted over the data link to the input of the apparatus.

Claims

1. Apparatus for decoding frames from a data link, each frame having multiple data characters, said apparatus comprising:

a frame input connected to said data link for the receipt thereon of a received frame from the data link;

an expect/mask buffer, having a first portion for storing a reproduction of expected characters expected to be in said received frame, and a second portion for storing a mask indicating which bits of the characters of said received frame are to be compared to corresponding bits of said expected characters in the first portion;

compare means for comparing characters of said received frame to corresponding expected characters in the first portion of said expect/mask buffer as masked by said second portion;

a compare register connected to said compare means for storing the results of the comparison of said compare means;

a header buffer having multiple entries and being connected to said frame input, each entry thereof for storing characters of one of the frames received by said frame input; and

a compare buffer having multiple entries and being connected to said compare register, each entry thereof for storing the contents of said compare register resulting from the comparison by said compare means for the corresponding frame entry in said header buffer.

2. The apparatus of claim 1 further comprising a state machine connected to said frame input, said state machine having a summary byte register and examining means for examining said received frame and providing a plurality of frame indicators to said summary byte register for storing said plurality of frame indicators therein as said received frame is examined by said examining means.

3. The apparatus of claim 2 wherein said state machine further comprises an alternate byte register for storing a plurality of error indicators and error detecting means for detecting errors in said received frame and providing a plurality of error indicators to said alternate compare byte register for storing said plurality of error indicators therein as said received frame is examined by said examining means.

4. The apparatus of claim 3 wherein said state machine further comprises an interface control check register for storing control checks, and control check detecting means for detecting control checks in said received frame and providing said control checks to said interface control check register for storing said control checks therein.

5. The apparatus of claim 3 wherein said header buffer has a data port and a write address port, said apparatus further comprising a header buffer write pointer connected to the write address port of said header buffer, said summary byte register being connected to the data port of said header buffer such that the contents of said summary byte register is written into a specified entry of said header buffer as determined by said header buffer write pointer after said received frame has been received by said frame input.

6. The apparatus of claim 5 wherein said compare buffer has a write address port and a data port, said apparatus further comprising a compare buffer write pointer connected to the write address port of said compare buffer and said alternate compare byte register being connected to the data port of said compare buffer for writing the contents of said alternate compare byte register into a specified entry of said compare buffer as determined by the contents of said header buffer write pointer, and write control means in said error detecting means for causing the contents of said alternate compare byte buffer to be written into said specified entry of said compare buffer instead of said compare register means when an error is detected in said received frame.

7. The apparatus of claim 6 wherein said header buffer has a read address port and said compare buffer has a read address port, said apparatus further comprising a header buffer read pointer connected to said read address port of said header buffer for reading the contents of a specified entry of said header buffer;

a microprocessor means connected to said header buffer read pointer for reading the contents of said header buffer for processing by said microprocessor means;

a compare buffer read pointer connected to the read address port of said compare buffer for reading the contents of a specified entry of said compare buffer as determined by said compare buffer read pointer for processing by said microprocessor means; and

pointer compare means having a first input connected to said compare write buffer and a second input connected to said compare buffer read pointer for comparing the contents of said compare buffer write pointer and said compare buffer read pointer for determining if there are entries in said header buffer and compare buffer which is queued work that has not been read by said microprocessor means.

8. The apparatus of claim 7 further comprising an error code checking circuit connected to said frame input, said error code checking circuit having means for calculating an error code from the characters in said received frame and comparing the result with an error detecting code recorded in said received frame, said error code checking circuit having an output connected to said state machine for reporting a mismatch in the calculated error code and the recorded error code.

9. The apparatus of claim 1 wherein said received frame is a data frame including a header portion having multiple bytes, said apparatus further comprising data frame recognition means connected to said frame input for controlling which bytes of said header portion are compared by said compare means for detecting the receipt of a data frame.

10. The apparatus of claim 9 further comprising data buffer means connected to said frame input for storing data from the frame received by said frame input;

LOAD DATA BUFFER signal generating means in said data frame recognition means for generating a LOAD DATA BUFFER signal when a data frame is recognized; and

state machine means connected to said LOAD DATA BUFFER signal generating means said state machine means for loading data from the data frame into said data buffer responsive to said LOAD DATA BUFFER signal.

11. The apparatus of claim 10 wherein said header portion includes a specific number of header bytes and a specific number of total bytes, and said data recognition circuit includes an X count register for containing a value equal to the number of said header bytes;

a Y count register for containing a value equal to the total number of bytes in said header portion; and

compare control means connected to said X count and said Y count registers for allowing the comparison of bytes received by said frame input to be compared until the number of bytes received equals to the value contained in said X count register, and for preventing comparison of bytes received by said frame input when the number of bytes received is greater than the value contained in the X count register but less than the value contained in the Y count register.

12. The apparatus of claim 11 further comprising a DMASK register connected to said frame input, said DMASK register for masking the expect portion of said expect/mask buffer to determine if the contents of the frame received by said frame input is a data frame.

13. The apparatus of claim 8 further comprising a compare invalid register for containing multiple bits, each bit contained therein having a first state indicating that a compare is invalid and a second state indicating that the compare is valid;

a bit decoder connected to the write address port of said header buffer, said bit decoder for resetting to its second state, a bit corresponding to the address of said header buffer when the beginning of a frame is received by said frame input means; and

bit selector means connected to the read address input of said compare buffer for selecting the bit of said compare invalid register which corresponds to the read address of said compare buffer such that the bit selected by said bit selector indicates if the entry in said compare buffer is valid or invalid.