Double gate static induction thyristor

• US 5,027,180 A
• Filed: 10/18/1989
• Issued: 06/25/1991
• Est. Priority Date: 12/11/1986
• Status: Expired due to Term

• Current Assignee: Mitsubishi Electric Corporation
• Original Assignee: Mitsubishi Electric Corporation
• Inventors: Kondoh, Hisao, Nishizawa, Jun-ichi
• Primary Examiner(s): Hille, Rolf
• Assistant Examiner(s): LOKE, STEVEN HO YIN
• Application Number:
  US07/423,661
• Time in Patent Office: 615 Days
• Field of Search: 357/22, 357/38, 357/39, 357/56
• US Class Current: 257/266
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/7392 with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)

Abstract

A double gate static induction thyristor comprises a semiconductor substrate, a first gate region formed at a first principal surface of the substrate, and a first semiconductor region of a first conduction type formed on the same first principal surface. A second gate region is formed at a second principal surface of the substrate, and a second semiconductor region of a second conduction type is formed on the same second principal surface. Gate electrodes are formed on the first and second gate regions, and main electrodes are formed on the first and second semiconductor regions, so that portions of the semiconductor regions surrounded by the gate regions form a current path between the main electrodes. Further, impurity is deeply diffused in portions of the first and second gate regions formed with the gate electrodes.

Claims

1. A double gate static induction thyristor comprising a semiconductor substrate having first and second principal surfaces opposite to each other, a first gate region formed at the first principal surface of the semiconductor substrate, a first semiconductor region of a first conduction type formed on the first principal surface of the semiconductor substrate, a second gate region formed at the second principal surface of the semiconductor substrate, a second semiconductor region of a second conduction type opposite to the first conduction type and formed on the second principal surface of the semiconductor substrate, gate electrodes formed on the first and second gate regions, and main electrodes formed on the first and second semiconductor regions, portions of the semiconductor regions surrounded by the gate region forming a current path between the main electrodes, wherein the improvement is that each of the first and second gate regions has a first diffusion region positioned underneath the corresponding gate electrode in ohmic contact with the corresponding gate electrode, and a second diffusion region which extends from the first diffusion region toward a semiconductor region of the semiconductor substrate positioned between the main electrodes, a large part of the second diffusion regions is spaced away from the first diffusion region in a cross-sectional view along the direction of the current flow between said main electrodes, and is electrically connected to the first diffusion region, a diffusion depth of the first diffusion region from the surface in contact with the corresponding gate electrode being larger than that of the second diffusion region from the same level as the surface of the first diffusion region in contact with the corresponding gate electrode.

2. A thyristor as claimed in claim 1 wherein each of the first and second semiconductor regions is in the form of a mesa, and portions of the first and second gate regions exposed at the outside of the mesa-shaped first and second semiconductor regions are formed with the gate electrodes, the other portion of the first gate region being buried at a boundary between the substrate and the first semiconductor region, the other portion of the second gate region being buried at a boundary between the substrate and the second semiconductor region, said other portions of the first and second gate regions being respectively formed of impurity diffused regions having a diffusion depth smaller than that of said portions of the first and second gate regions formed with the gate electrodes.

3. A thyristor as claimed in claim 1 wherein each of the first and second semiconductor regions is in the form of a mesa, and all the first and second gate regions are exposed at the outside of the mesa-shaped first and second semiconductor regions.

4. A thyristor as claimed in claim 1 wherein the substrate includes a first semiconductor layer of the first conduction type and a second semiconductor layer of the second conduction type on the first layer with a p-n junction being formed between the first and second semiconductor layers, the first gate region and the first semiconductor region being formed at the first semiconductor layer, and the second gate region and the second semiconductor region being formed at the second semiconductor layer.