Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions
First Claim
1. An output logic circuit receiving a logic signal from a functional logic circuit and a clock signal coupled between the functional logic circuit and an input/output port, comprising:
- register means, connected to receive the logic signal and responsive to the clock signal, for storing said logic signal to provide a registered signal;
output select means, connected to receive the logic signal and the registered signal and responsive to an output select signal, for dynamically selecting said logic signal or said registered signal for supply as a selected signal to the input/output port;
feedback means for providing a feedback signal to the functional logic circuit, including a feedback select means, connected to receive the logic signal and the registered signal and responsive to a feedback select signal, for dynamically selecting said logic signal or said registered signal as the feedback signal;
the functional logic circuit includingmeans, in communication with said feedback select means, for dynamically providing said feedback select signal; and
means, in communication with said output select means, for dynamically providing said output select signal.
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Accused Products
Abstract
The present invention provides an output logic macrocell for controlling configuration of an output for an integrated circuit wich provides a logic signal including a register responsive to a clock signal for latching the logic signal to provide a registered signal. An output selector receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback path provides a feedback signal as data which is selected by a feedback selector responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable circuit, responsive to a clock enable signal, enables or disables the clock signal to clock the register. Accordingly, the register, the output selector, the feedback path, and the clock enable circuit are all dynamically controllable by respective control signals.
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Citations
27 Claims
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1. An output logic circuit receiving a logic signal from a functional logic circuit and a clock signal coupled between the functional logic circuit and an input/output port, comprising:
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register means, connected to receive the logic signal and responsive to the clock signal, for storing said logic signal to provide a registered signal; output select means, connected to receive the logic signal and the registered signal and responsive to an output select signal, for dynamically selecting said logic signal or said registered signal for supply as a selected signal to the input/output port; feedback means for providing a feedback signal to the functional logic circuit, including a feedback select means, connected to receive the logic signal and the registered signal and responsive to a feedback select signal, for dynamically selecting said logic signal or said registered signal as the feedback signal; the functional logic circuit including means, in communication with said feedback select means, for dynamically providing said feedback select signal; and means, in communication with said output select means, for dynamically providing said output select signal. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. In a programmable array logic device having a first plurality of logic cells for dynamically generating logic signals, a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, said logic signals and said combinatorial signals being dynamic signals, an output logic circuit receiving one of said combinatorial signals and a clock signal coupled between one of said second plurality of combinatorial means and an input/output port, comprising:
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clock enable means, coupled to receive the clock signal and responsive to a clock enable signal for dynamically enabling supply of the clock signal to a clock line; means, connected to the clock enable means and responsive to a plurality select signal, for dynamically selecting an active high or an active low polarity for the clock signal supplied to the clock line; register means, connected to the clock line and responsive to the clock signal on the clock line, for storing said one of said combinatorial signals; means for connecting a first pre-selected one of said dynamic signal as said clock enable signal to said clock enable means; and means for connecting a second pre-selected one of said dynamic signals as said polarity select signal to said means for selecting polarity.
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11. In a programmable array logic device having a first plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals;
- said logic signals and said combinatorial signals being dynamic signals, an output logic circuit receiving one of said combinatorial signals and a clock signal coupled between one of said second plurality of combinatorial means and an input/output port, comprising;
register means for storing said one of said combinatorial signals and providing a stored signal; means, coupled with said register means and responsive to a reset signal, for dynamically resetting the stored signal in said register means; output select means, connected to receive said one of said combinatorial signals and said stored signal, and responsive to an output select signal, for dynamically selecting said stored signal or said one of said combinatorial signals as a selected signal to the input/output port; means for connecting one of said dynamic signals as said output select signal to said output select means; and means for connecting another one of said dynamic signals as said reset signal to said means for resetting. - View Dependent Claims (12, 13, 14)
- said logic signals and said combinatorial signals being dynamic signals, an output logic circuit receiving one of said combinatorial signals and a clock signal coupled between one of said second plurality of combinatorial means and an input/output port, comprising;
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15. A programmable array logic device, receiving a clock signal and a plurality of data signals, having a plurality of input/output ports, comprising:
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a programmable logic cell array means responsive to the plurality of data signals for providing a set of logic signals; combinatorial means for combining a subset of said set of logic signals to provide a plurality of combinatorial signals, said logic signals and said combinatorial signals being dynamic signals; output logic means, receiving one of said combinatorial signals and the clock signal, coupled to one of the input/output ports for controlling the input/output port including register means, responsive to the clock signal, for storing said one combinatorial signal to provide a registered signal; output select means, connected to receive said one combinatorial signal and said registered signal and responsive to an output select signal, for dynamically selecting said combinatorial signal or said registered signal as a selected signal, feedback means for providing a feedback signal as data to said programmable logic cell array means including a feedback select means, connected to receive said one combinatorial signal and said registered signal and responsive to a feedback select signal, for dynamically selecting said one combinatorial signal or said registered signal as said feedback signal, and clock signal enable means, connected to receive said clock signal and to said register means and responsive to a clock enable signal, for dynamically enabling said clock signal to clock said register means; output enable means, connected to receive said selected signal and to the one input/output port and responsive to an output enable signal, for enabling the selected signal from said output select means as an output signal at the one input/output port, means for connecting a first of said dynamic signals as the clock enable signal to the clock signal enable means; means for connecting a second of said dynamic signals as the feedback select signal to the feedback select means; means for connecting a third of said dynamic signals as the output select signal to the output select means; means for connecting a fourth of said dynamic signals as the output enable signal to the output enable means. - View Dependent Claims (16, 17, 18, 19, 20, 21)
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22. In a programmable array logic device having a first plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, the logic signals and combinatorial signals being dynamic signals, an output logic circuit, receiving one of said combinatorial signals and a clock signal, coupled between one of said second plurality of combinatorial means and an input/output port, comprising:
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register means for storage said one of said combinatorial signals and providing a registered signal; output select means, connected to receive said one of said combinatorial signals and said registered signal and responsive to an output select signal, for dynamically selecting said registered signal or said one of said combinatorial signals as a selected signal for supply to the input/output port; feedback means for providing a feedback signal to one or more of the logic cells including a feedback select means, connected to receive said one of said combinatorial signals and said registered signal and responsive to a feedback select signal, for dynamically selecting said one of said combinatorial signals or said registered signal as the feedback signal; means for connecting one of said dynamic signals as said output select signal to said output select means; and means for connecting another one of said dynamic signals as said feedback select signal to said feedback select means. - View Dependent Claims (23, 24, 25, 26)
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27. In a programmable array logic device having a first plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, the logic signals and combinatorial signals being dynamic signals, an output logic circuit, receiving one of said combinatorial signals and a clock signal, coupled between one of said second plurality of combinatorial means and an input/output port, comprising:
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register means for storing said one of said combinatorial signals providing a registered signal; output select means, connected to receive said one of said combinatorial signals and said register signal and responsive to an output select signal, for dynamically selecting said registered signal or said one of said combinatorial signals as a selected signal for supply to the input/output port; feedback means coupled to said register means for providing said registered signal as a feedback signal to one or more of the logic cells; means for connecting one of said dynamic signals as said output select signal to said output select means; means connected between said input/output port and one or more of said logic cells, for providing a data signal from said input/output port as an input signal to said one or more logic cells; output enable means, coupled to said output select means and said input/output port and responsive to an output enable signal, for dynamically enabling supply of the selected signal from said output select means as an output data signal to the input/output port; and means for connecting another of said dynamic signals as said output enable signal to said output enable means.
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Specification