Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions

• US 5,027,315 A
• Filed: 08/30/1989
• Issued: 06/25/1991
• Est. Priority Date: 09/28/1984
• Status: Expired due to Term

• Current Assignee: Lattice Semiconductor Corporation
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Agrawal, Om P., Brcich, Joseph A.
• Primary Examiner(s): Lee, Thomas C.
• Application Number:
  US07/401,528
• Time in Patent Office: 664 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/716, 340/825.79, 340/825.83, 340/825.84, 340/825.86, 307/465, 307/466, 307/468, 307/601, 307/602, 307/605, 307/593
• US Class Current: 326/38
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/17716 with synchronous operation, i.e. using clock signals, e.g. of I/O or coupling register H03K19/17712 takes precedence

Abstract

The present invention provides an output logic macrocell for controlling configuration of an output for an integrated circuit wich provides a logic signal including a register responsive to a clock signal for latching the logic signal to provide a registered signal. An output selector receives both the logic signal and the registered signal and selects responsive to an output select signal, either the logic signal or the registered signal. A feedback path provides a feedback signal as data which is selected by a feedback selector responsive to a feedback select signal for selecting the logic signal or the registered signal as the feedback signal. Further, a clock signal enable circuit, responsive to a clock enable signal, enables or disables the clock signal to clock the register. Accordingly, the register, the output selector, the feedback path, and the clock enable circuit are all dynamically controllable by respective control signals.

Claims

1. An output logic circuit receiving a logic signal from a functional logic circuit and a clock signal coupled between the functional logic circuit and an input/output port, comprising:

register means, connected to receive the logic signal and responsive to the clock signal, for storing said logic signal to provide a registered signal;

output select means, connected to receive the logic signal and the registered signal and responsive to an output select signal, for dynamically selecting said logic signal or said registered signal for supply as a selected signal to the input/output port;

feedback means for providing a feedback signal to the functional logic circuit, including a feedback select means, connected to receive the logic signal and the registered signal and responsive to a feedback select signal, for dynamically selecting said logic signal or said registered signal as the feedback signal;

the functional logic circuit including

means, in communication with said feedback select means, for dynamically providing said feedback select signal; and

means, in communication with said output select means, for dynamically providing said output select signal.

2. The circuit of claim 1, wherein said register means includes:

means, responsive to a reset signal, for asynchronous reset of said register means; and

the functional logic circuit includes

means, in communication with the means for asynchronous reset, for dynamically providing said reset signal.

3. The circuit of claim 1, wherein said register means includes:

means, responsive to a preset signal, for preset of said register means, and the functional logic circuit includes

means, in communication with the means for preset, for dynamically providing said preset signal.

4. The circuit of claim 1, further including:

output enable means, coupled between said output select means and said input/output port and responsive to an output enable signal, for dynamically enabling the selected signal from said output select means as an output signal to the input/output port; and

the functional logic circuit includes

means, in communication with the output enable means, for dynamically providing the output enable signal.

5. The output logic circuit of claim 1, further including:

clock signal enable means, coupled to the register means and responsive to a clock enable signal, for dynamically enabling said clock signal to clock said register means; and

the functional logic circuit includes

means, in communication with said clock signal enable means, for dynamically providing said clock enable signal.

6. The circuit of claim 5, wherein said clock enable means includes:

means, coupled to receive the clock signal, for programmably selecting the polarity of the clock signal.

7. The circuit of claim 1, further including:

means, coupled to receive the clock signal and to the registered means and responsive to a polarity select signal, for dynamically selecting the polarity of the clock signal; and

the functional logic circuit includes

means, in communication with the means for selecting the polarity, for dynamically providing said polarity select signal.

8. The circuit of claim 1, wherein:

said register means provides said registered signal and a complement of said registered signal; and

further including

means, connected to receive said logic signal, for complementing said logic signal to provide a complement of said logic signal; and

said output select means is further connected to receive said complement of said logic signal and said complement of said registered signal and dynamically selects said registered signal, said complement of said registered signal, said logic signal, or said complement of said logic signal as said output signal.

9. The circuit of claim 1, further comprising:

means, in communication with the input/output port, for providing data signals from the input/output port as feedback to the functional logic circuit.

10. In a programmable array logic device having a first plurality of logic cells for dynamically generating logic signals, a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, said logic signals and said combinatorial signals being dynamic signals, an output logic circuit receiving one of said combinatorial signals and a clock signal coupled between one of said second plurality of combinatorial means and an input/output port, comprising:

clock enable means, coupled to receive the clock signal and responsive to a clock enable signal for dynamically enabling supply of the clock signal to a clock line;

means, connected to the clock enable means and responsive to a plurality select signal, for dynamically selecting an active high or an active low polarity for the clock signal supplied to the clock line;

register means, connected to the clock line and responsive to the clock signal on the clock line, for storing said one of said combinatorial signals;

means for connecting a first pre-selected one of said dynamic signal as said clock enable signal to said clock enable means; and

means for connecting a second pre-selected one of said dynamic signals as said polarity select signal to said means for selecting polarity.

11. In a programmable array logic device having a first plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals;

said logic signals and said combinatorial signals being dynamic signals, an output logic circuit receiving one of said combinatorial signals and a clock signal coupled between one of said second plurality of combinatorial means and an input/output port, comprising;

register means for storing said one of said combinatorial signals and providing a stored signal;

means, coupled with said register means and responsive to a reset signal, for dynamically resetting the stored signal in said register means;

output select means, connected to receive said one of said combinatorial signals and said stored signal, and responsive to an output select signal, for dynamically selecting said stored signal or said one of said combinatorial signals as a selected signal to the input/output port;

means for connecting one of said dynamic signals as said output select signal to said output select means; and

means for connecting another one of said dynamic signals as said reset signal to said means for resetting.

12. The circuit of claim 11, wherein:

said stored means provides said registered signal and a complement of said stored signal; and

further including

means, connected to receive said one of said combinatorial signals, for complementing said one of said combinatorial signals to provide a complement of said one combinatorial signal; and

said output select means is further connected to receive said complement of said stored signal and said complement of said one combinatorial signal and selects said stored signal, said complement of said stored signal, said one combinatorial signal, or said complement of said one combinatorial signal as said selected signal.

13. The circuit of claim 11, further comprising:

output enable means, coupled between said output select means and said input/output port and responsive to an output enable signal for dynamically enabling the selected signal as an output signal at said input/output port; and

means for connecting another of said combinatorial signals as said output enable signal to said output enable means.

14. The circuit of claim 13, further comprising:

means, connected between said input/output port and one or more of said logic cells, for providing a data signal from said input/output port as an input signal to said one or more logic cells.

15. A programmable array logic device, receiving a clock signal and a plurality of data signals, having a plurality of input/output ports, comprising:

a programmable logic cell array means responsive to the plurality of data signals for providing a set of logic signals;

combinatorial means for combining a subset of said set of logic signals to provide a plurality of combinatorial signals, said logic signals and said combinatorial signals being dynamic signals;

output logic means, receiving one of said combinatorial signals and the clock signal, coupled to one of the input/output ports for controlling the input/output port including

register means, responsive to the clock signal, for storing said one combinatorial signal to provide a registered signal;

output select means, connected to receive said one combinatorial signal and said registered signal and responsive to an output select signal, for dynamically selecting said combinatorial signal or said registered signal as a selected signal,

feedback means for providing a feedback signal as data to said programmable logic cell array means including a feedback select means, connected to receive said one combinatorial signal and said registered signal and responsive to a feedback select signal, for dynamically selecting said one combinatorial signal or said registered signal as said feedback signal, and

clock signal enable means, connected to receive said clock signal and to said register means and responsive to a clock enable signal, for dynamically enabling said clock signal to clock said register means;

output enable means, connected to receive said selected signal and to the one input/output port and responsive to an output enable signal, for enabling the selected signal from said output select means as an output signal at the one input/output port,

means for connecting a first of said dynamic signals as the clock enable signal to the clock signal enable means;

means for connecting a second of said dynamic signals as the feedback select signal to the feedback select means;

means for connecting a third of said dynamic signals as the output select signal to the output select means;

means for connecting a fourth of said dynamic signals as the output enable signal to the output enable means.

16. The device of claim 15, wherein said register means of said output logic means includes:

means, responsive to a reset signal, for asynchronous reset of said register means, and

means for connecting a fifth of said dynamic signals as said reset signal to said means for asynchronous reset.

17. The device of claim 15, wherein said register means of said output logic means includes:

means, responsive to a preset signal, for preset of said register means, and

means, for connecting a fifth of said dynamic signals as said preset signal to said means for preset.

18. The circuit of claim 15, wherein said clock enable means includes:

means coupled to receive the clock signal for programmably controlling the polarity of said clock signal.

19. The circuit of claim 15, further including:

means, coupled to receive the clock signal and to the register means and responsive to a polarity select signal, for dynamically selecting the polarity of the clock signal; and

means for connecting a fifth of said dynamic signals as said polarity selected signal to said means for selecting the polarity.

20. The circuit of claim 15, wherein:

said register means provides said registered signal and a complement of said registered signal; and

further including

means, connected to receive said one combinatorial signal, for complementing said one combinatorial signal to provide a complement of said one combinatorial signal; and

said output select means is further connected to receive said complement of said registered signal and said complement of said one combinatorial signal and dynamically selects said registered signal, said complement of said registered signal, said one combinatorial signal, or said complement of said one combinatorial signal as said selected signal.

21. The circuit of claim 15, further comprising:

means, connected between said one input/output port and said programmable logic cell array means, for providing data signals from said one input/output port to said programmable logic cell array means.

22. In a programmable array logic device having a first plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, the logic signals and combinatorial signals being dynamic signals, an output logic circuit, receiving one of said combinatorial signals and a clock signal, coupled between one of said second plurality of combinatorial means and an input/output port, comprising:

register means for storage said one of said combinatorial signals and providing a registered signal;

output select means, connected to receive said one of said combinatorial signals and said registered signal and responsive to an output select signal, for dynamically selecting said registered signal or said one of said combinatorial signals as a selected signal for supply to the input/output port;

feedback means for providing a feedback signal to one or more of the logic cells including a feedback select means, connected to receive said one of said combinatorial signals and said registered signal and responsive to a feedback select signal, for dynamically selecting said one of said combinatorial signals or said registered signal as the feedback signal;

means for connecting one of said dynamic signals as said output select signal to said output select means; and

means for connecting another one of said dynamic signals as said feedback select signal to said feedback select means.

23. The circuit of claim 22 further comprising:

means, connected between said input/output port and one or more of said logic cells, for providing a data signal from said input/output port as an input signal to said one or more logic cells.

24. The circuit of claim 22 further comprising:

output enable means, coupled between said output select means and said input/output port and responsive to an output enable signal for dynamically enabling supply of the selected signal from said output select means as an output signal to the input/output port; and

means for connecting another of said combinatorial signals as said output enable signal to said output enable means.

25. The circuit of claim 24 further comprising:

output enable means, coupled between said output select means and said input/output port and responsive to an output enable signal for enabling supply of the selected signal from said output select means as an output signal to the input/output port; and

means for connecting another of said combinatorial signals as said output enable signal to said output enable means.

26. The circuit of claim 22 further comprising:

means, coupled to receive the clock signal and to the register means and responsive to a polarity select signal, for selecting the polarity of the clock signal; and

means for connecting a third of said dynamic signals as said polarity select signal to said means for selecting the polarity.

27. In a programmable array logic device having a first plurality of logic cells for dynamically generating logic signals, and a second plurality of combinatorial means for combining a subset of said logic signals to generate a plurality of combinatorial signals, the logic signals and combinatorial signals being dynamic signals, an output logic circuit, receiving one of said combinatorial signals and a clock signal, coupled between one of said second plurality of combinatorial means and an input/output port, comprising:

register means for storing said one of said combinatorial signals providing a registered signal;

output select means, connected to receive said one of said combinatorial signals and said register signal and responsive to an output select signal, for dynamically selecting said registered signal or said one of said combinatorial signals as a selected signal for supply to the input/output port;

feedback means coupled to said register means for providing said registered signal as a feedback signal to one or more of the logic cells;

means for connecting one of said dynamic signals as said output select signal to said output select means;

means connected between said input/output port and one or more of said logic cells, for providing a data signal from said input/output port as an input signal to said one or more logic cells;

output enable means, coupled to said output select means and said input/output port and responsive to an output enable signal, for dynamically enabling supply of the selected signal from said output select means as an output data signal to the input/output port; and

means for connecting another of said dynamic signals as said output enable signal to said output enable means.