EPROM circuit having enhanced programmability and improved speed and reliability

• US 5,027,320 A
• Filed: 09/22/1989
• Issued: 06/25/1991
• Est. Priority Date: 09/22/1989
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Prickett, Bruce, Pathak, Saroj
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US07/410,951
• Time in Patent Office: 641 Days
• Field of Search: 365/104, 365/185, 365/189.06
• US Class Current: 365/185.23
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits

Abstract

The present invention relates to an MOS integrated circuit employing a plurality of floating gate type, erasable, programmable read-only memory (EPROM) devices. The improvement of the invention comprises a clamp coupled to the control gates of the EPROMs, the clamp being adapted to clamp the voltage on these gates in the range of the typical supply voltage for the circuit, whereby, after an EPROM cell is properly charged, it will continue to read out as a properly charged cell even though some of the actual charge on its floating gate may have leaked.

Claims

1. In an MOS integrated circuit having a plurality of floating gate type erasable, programmable read-only memory devices, the improvement comprising a clamping means coupled to the control gates of said memory devices, said clamping means being adapted, as said memory device is being charged to a predetermined voltage by the application of a voltage to its control gates, to clamp the resulting voltage on said control gates below the maximum supply voltage for said circuit, whereby, after said memory device has been properly charged, during a read operation said memory device will continue to read out as a properly charged memory device even though some of the actual charge on its floating gate subsequently may have leaked.

2. The improvement in the floating gate memory circuit of claim 1 further characterized by said clamping voltage being applied to the control gate of said memory device through a passgate transistor.

3. The improvement in the floating gate memory circuit of claim 2 further characterized by said passgate transistor being a depletion mode device.

4. The improvement in the floating gate memory circuit of claim 1 further characterized by the voltage on said clamping means being taken from a node on said integrated circuit the voltage on which varies proportionally to the threshold voltage and current of the other transistors on the integrated circuit in accordance with processing and temperature variations.