Receiver frequency offset bias circuit for TDM radios

• US 5,027,352 A
• Filed: 01/05/1989
• Issued: 06/25/1991
• Est. Priority Date: 01/05/1989
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Goode, Steven H.
• Primary Examiner(s): Olms, Douglas W.
• Assistant Examiner(s): Marcelo, Melvin
• Application Number:
  US07/293,285
• Time in Patent Office: 901 Days
• Field of Search: 370/100.1, 370/110.1, 455/62, 455/183, 455/231, 455/214, 455/312, 455/334, 375/111, 375/113, 375/114, 375/76
• US Class Current: 370/345
• CPC Class Codes: H04L 27/142 Compensating direct current components occurring during the demodulation and which are caused by mistuning

Abstract

An improved bias control circuit (FIG. 2) is disclosed for a radio receiver (122) used in a communication system wherein a signalling preamble is sent prior to sending other information. The bias circuit (140) rapidly determines the DC voltage level representing the average frequency of the received signalling preamble (215), develops a DC bias voltage (275) proportional to the error in frequency between the receiver and the transmitted signal, and then selectively applies this bias voltage to the series coupling capacitor (240) located between the receiver detector (121) and the receiver processing circuitry (123). The circuit is adapted for a 0.2 GMSK receiver in a TDMA communication system, where a known 1100 bit synchronization preamble is sent in each user'"'"'s TDM time slot.

Claims

1. A bias control circuit for a radio receiver used in a communication system wherein a signalling preamble is sent to said receiver prior to sending other information, said bias control circuit comprising:

a coupling capacitor having an input terminal and an output terminal;

means for selectively coupling said capacitor input terminal to a received input signal in response to a control signal;

means for biasing said capacitor input terminal to a desired voltage in response to said control signal; and

controller means for providing said control signal in response to the reception of said signalling preamble,

whereby said coupling capacitor is properly biased for the subsequent reception of said other information.

2. The bias control circuit according to claim 1, further comprising means for maintaining said capacitor output terminal at a desired voltage in response to said biasing means biasing said capacitor input terminal.

3. The bias control circuit according to claim 1, further comprising means for biasing said capacitor output terminal to a desired voltage in response to said control signal.

4. The bias control circuit according to claim 1, further comprising means for determining the average DC voltage level of said received input signal.

5. The bias control circuit according to claim 4, wherein said biasing means applies said average DC voltage level to said capacitor input terminal.

6. The bias control circuit according to claim 1, wherein said signalling preamble exhibits a balanced AC waveform.

7. The bias control circuit according to claim 1, wherein said selective coupling means effectively isolates said capacitor input terminal from said a received input signal when said biasing means biases said capacitor input terminal.

8. The bias control circuit according to claim 1, wherein the value of said coupling capacitor in said bias control circuit is large enough to pass all frequencies of said received input signal above 5 Hertz.

9. A circuit for coupling an AC signal from a input node to a output node, said circuit comprising:

a capacitor having first and second terminals;

first switching means for controllably coupling said input node to said first terminal;

means for determining the average DC voltage level of said AC signal at said input node;

second switching means for controllably applying said average DC voltage to said first terminal;

third switching means for controllably applying a reference DC voltage to said second terminal;

means for coupling said second terminal to said output node; and

means for controlling said first, second, and third switching means such that said average DC voltage is applied to said capacitor first terminal only during a first time period, and such that said AC signal is coupled from said input node to said output node only during a second time period not overlapping said first time period.

10. The coupling circuit according to claim 9, wherein said controlling means controls said first, second, and third switching means such that said reference DC voltage is applied to said capacitor second terminal during said first time period.

11. The coupling circuit according to claim 9, wherein said third switching means includes feedback means for monitoring the voltage at said capacitor second terminal, and for controllably applying a difference DC voltage to said second terminal, said difference DC voltage being proportional to the difference between said reference DC voltage and the voltage at said second terminal.

12. The coupling circuit according to claim 9, wherein the value of said capacitor is large enough to pass all frequencies of said received input signal above 5 Hertz.

13. The coupling circuit according to claim 9, wherein said first time period is shorter than 5 milliseconds.

14. The coupling circuit according to claim 9, wherein said first, second, and third switching means include CMOS switch devices.

15. A method of receiving coded information in a radio receiver having a signal processor for decoding said information, said method comprising the steps of:

(a) demodulating a modulated radio frequency (RF) carrier in a radio receiver, thereby providing a received signal;

(b) determining the average DC voltage level of said received signal during a first time period;

(c) determining the preferred DC reference voltage level of said signal processor for optimal information decoding;

(d) precharging a capacitor to a DC precharge voltage during a second time period;

(e) series coupling said received signal from said receiver to said signal processor through said precharged capacitor; and

(f) decoding information from said received signal in said signal processor during a third time period, whereby said third time period does not overlap said second time period.

16. The method according to claim 15, wherein step (d) further comprises the steps of:

(1) providing said average DC voltage via a low impedance source to the side of said capacitor which is coupled to said received signal; and

(2) providing said DC reference voltage via a low impedance source to the other side of said capacitor during the above step 1.

17. The method according to claim 15, wherein said third time period occurs immediately after said second time period.

18. The method according to claim 15, wherein said information is modulated on said RF carrier utilizing Gaussian minimum shift keying.

19. The method according to claim 15, wherein said radio receiver is adapted to operate in a Time Division Multiplex radio system.

20. The method according to claim 19, wherein said first time period generally corresponds to each TDM bit synchronization word time slot.

21. The method according to claim 19, wherein said third time period generally corresponds to each TDM vocoded speech information time slot.

22. The method according to claim 15, wherein said average DC voltage level is determined by integrating said received signal over an integration time period which is shorter than said first time period.

23. The method according to claim 15, wherein said information is coded such that said received signal exhibits a balanced waveform during said first time period.

24. The method according to claim 15, wherein the value of said capacitor is large enough to pass all frequencies of said received signal above 5 Hertz.

25. The method according to claim 15, wherein said second time period is shorter than 5 milliseconds.

26. A radio receiver used in a communication system wherein a signalling preamble is sent prior to sending other information, said radio receiver comprising:

receiver means for receiving a radio frequency (RF) carrier, thereby providing a received signal;

signal processing means for decoding information from said received signal, said signal processing means having a preferred DC reference voltage level for optimal information decoding;

capacitor means for AC coupling said received signal from said receiver means to said signal processing means;

averaging means for determining the average DC voltage level of said received signal during the time period when said signalling preamble is being received; and

biasing means for selectively applying a DC biasing voltage to said capacitor means in response to said averaging means at times other than when said information is being received.

27. The radio receiver according to claim 26, wherein said biasing means includes:

means for providing said average DC voltage via a low impedance source to the side of said capacitor which is coupled to said receiver means; and

means for providing said DC reference voltage via a low impedance source to the side of said capacitor which is coupled to said signal processing means.

28. The radio receiver according to claim 26, wherein said information is modulated on said RF carrier utilizing Gaussian minimum shift keying.

29. The radio receiver according to claim 26, wherein said radio receiver is adapted to operate in a Time Division Multiplex radio system.

30. The radio receiver according to claim 29, wherein said preamble time period generally corresponds to each TDM bit synchronization word time slot.

31. The radio receiver according to claim 26, wherein said average DC voltage level is determined by integrating said received signal over an integration time period which is shorter than said preamble time period.

32. The radio receiver according to claim 26, wherein said information is coded such that said received signal exhibits a balanced waveform during said preamble time period.

33. The radio receiver according to claim 26, wherein the value of said capacitor is large enough to pass all frequencies of said received signal above 5 Hertz.