Identification transponder circuit

• US 5,028,918 A
• Filed: 12/18/1989
• Issued: 07/02/1991
• Est. Priority Date: 12/18/1989
• Status: Expired due to Fees

• Current Assignee: Daily Equipment Co. (Mitsubishi Heavy Industries, Ltd.)
• Original Assignee: Daily Equipment Co. (Mitsubishi Heavy Industries, Ltd.)
• Inventors: Giles, Thomas E., Reining, William N.
• Primary Examiner(s): Yusko, Donald J.
• Assistant Examiner(s): Magistre, Dervis
• Application Number:
  US07/452,538
• Time in Patent Office: 561 Days
• Field of Search: 340/505, 340/572, 340/573, 340/825.3, 340/825.31, 340/825.34, 340/825.54, 340/825.57, 340/825.58, 119/51.02, 119/155, 128/903, 455/16, 455/41, 235/449, 235/450, 342/51, 342/44
• US Class Current: 340/10.51
• CPC Class Codes: G06K 19/0723 the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs

Abstract

A phase encoded transponder circuit is disclosed which may be a passive device capable of response to an interrogating signal and is capable of transmitting an individual unique identification code. The transponder is particularly useful for identifying an individual, such as an animal, associated with the transponder. The code is stored in a memory device which is also loaded with several flags to actuate optional states of the system. One set of flags enable a state in which up to three additional words of the message are transmitted by the transponder. These additional words may be fixed internal data or variable data sent to the circuit by an external data module. Another state permits the importation into the transponder of an unlimited stream of external data from a connected device, so that the transponder can be used to transmit a variety of data about the individual associated with the transponder to the interrogation station.

Claims

1. A state variable phase encoded transponder circuit for use in a device for the transmission of identification and other data from the device to an interrogating unit comprising

a memory portion containing stored data including an identification code and three data word enable flags and an external data enable flag;

a data bus connected to carry data from the memory portion;

timing circuitry connected to address the memory portion to access stored data including the identification code therein and to cause it to be transferred from the memory in a series of words in parallel on the data bus;

parallel to serial data conversion means connected to the data bus to convert data thereon into a serial phase encoded data stream;

three data enable latches connected to the data bus to test for the external data word enable flags;

a parallel input external data bus connected so as to be capable of providing external data to the data bus;

gating means connected for operating the external data bus only when the data enable latch has been activated by the external data enable flag, the gating means being further connected to the timing means to enable the external data bus only during times which do not conflict with the transmission of the identification code from the memory so that the identification code and parallel input data may be converted by the parallel to serial conversion means into a common serial data stream; and

wherein the message transmitted by the circuit is up to eight words in length, and wherein the other data to be transmitted is any combination of the fifth, sixth and seventh words of the message.

2. A state variable phase encoded transponder circuit for use in a device for the transmission of identification and other data from the device to an interrogating unit comprising

a memory portion containing stored data including an identification code and one or more data word enable flags and external data enable flags;

a data bus connecting to the memory portion to carry data therefrom;

timing circuitry to address the memory portion to access stored data including the identification code therein and to cause it to be transferred from the memory to the data bus in a series of words in parallel;

parallel to serial data conversion means connected to the data bus to convert data thereon into a serial phase encoded data stream;

at least one data enable latch connected to the data bus to test for the external data word enable flag;

a parallel input external data bust connected to input its data onto the data bus; and

gating means connected for operating the external data bus only when the data enable latch has been activated by the external data enable flag, the gating means being further connected to the timing means to enable the external data bus only during times which do not conflict with the transmission of the identification code from the memory so that the identification code and parallel input data may be converted by the parallel to serial conversion means into a common serial data stream.

3. A state variable phase encoded transponder circuit for use in a device for the transmission of identification and other data from the device to an interrogating unit comprising

a memory portion containing stored data including an identification code and one or more data word enable flags and external data enable flags;

a data bus connected to carry data from the memory portion;

timing circuitry connected to address the memory portion to access stored data including the identification code therein and to cause it to be transferred from the memory in a series of words in parallel on the data bus connected to the data bus;

parallel to serial data conversion means connected to the data bus to convert data thereon into a serial phase encoded data stream;

three data enable latches connected to the data bus to test for the external data word enable flag;

a priority encoder, the inputs to which are the outputs of the data word enable latches;

a parallel input external data bus;

gating means connected for operating the external data bus only when one of the data enable latches has been activated by the external data enable flag, the gating means being further connected to the timing means to enable the external data bus only during times which do not conflict with the transmission of the identification code from the memory so that the identification code and parallel input data may be converted by the parallel to serial conversion means into a common serial data stream; and

the output of the priority encoder being connected as externally accessible address lines which are adapted to be connected so that an external device applying data to the parallel input external data bus can be addressed on a word by word basis.

4. A phase encoded transponder circuit as claimed in claim 3 wherein the memory is a programmable read-only memory.

5. A state variable phase encoded transponder circuit for use in a device for the transmission of identification and other data from the device to an interrogating unit comprising

a memory portion containing stored data including an identification code and one or more data word enable flags and external data enable flags;

a data bus connected to carry data from the memory portion;

timing circuitry to address the memory portion to access stored data including the identification code therein and to cause it to be transferred from the memory in a series of words in parallel to the data bus;

parallel to serial data conversion means connected to the data bus to convert data thereon into a serial phase encoded data stream;

at last one data enable latch connected to the data bus to test for the external data word enable flag;

a parallel input external data bus connected so as to be capable of presenting external data to the data bus;

grating means connected for operating the external data bus only when the data enable latch has been activated by the external data enable flag, the gating means being further connected to the timing means to enable the external data bus only during times which do not conflict with the transmission of the identification code from the memory so that the identification code and parallel input data may be converted by the parallel to serial conversion means into a common serial data stream; and

wherein the circuit transmits an eight word message and the gating means is connected to the timing circuitry to only permit the input external data bus to be enabled during the second four words of the message transmission.

6. A phase encoded transponder circuit as claimed in claim 5 wherein there is further a parity generator in the parallel to serial conversion means to generate a parity bit at the end of end word transmission.

7. A state variable phase encoded transponder circuit for use in a device for the transmission of identification and other data from the device to an interrogating unit comprising

a memory portion containing stored data including an identification code and one or more data word enable flags and external data enable flags;

a data bus connected to carry data from the memory portion;

timing circuitry connected to address the memory portion to access stored data including the identification code therein and to cause it to be transferred from the memory in a series of words in parallel on the data bus;

parallel to serial data conversion means connected to the data bus to convert data thereon into a serial phase encoded data stream;

at least one data enable latch connected to the data bus to test for the external data word enable flag;

a parallel input external data bus connected so as to be capable of presenting external data to the data bus;

grating means connected for operating the external data bus only when the data enable latch has been activated by the external data enable flag, the gating means being further connected to the timing means to enable the external data bus only during times which do not conflict with the transmission of the identification code from the memory so that the identification code and parallel input data may be converted by the parallel to serial conversion means into a common serial data stream; and

an exclusive-OR word generator circuit connected to receive input data from the data bus to perform an exclusive-OR function with the words on the data bus, the output of the exclusive-Or circuit also connected to the data bus and being selected by the timing means to be presented to the data bus so that the cumulative exclusive-OR product word is presented to the data bus for transmission as a word of the transmitted message.

8. A state variable phase encoded transponder circuit for use in a device for the transmission of identification and other data from the device to an interrogating unit comprising

a memory portion containing stored data including an identification code and one or more data word enable flags and external data enable flags;

a data bus connected to carry data from the memory portion;

timing circuitry to address the memory portion to access stored data including the identification code therein and to cause it to be transferred from the memory in a series of words in parallel on the data bus;

parallel to serial data conversion means connected to the data bus to convert the data thereon into a serial phase encoded data stream;

at least one data enable latch connected to the data bus test for the external data word enable flag;

a parallel input external data bus connected to present external data to the data bus;

gating means connected for operating the external data bus only when the data enable latch has been activated by the external data enable flag, the gating means being further connected to the timing means to enable the external data bus only during times which do not conflict with the transmission of the identification code from the memory so that the identification code and parallel input data may be converted by the parallel to serial conversion means into a common serial data stream; and

a predetermined period timer which is connected to an external data latching means so as to permit, when the predetermined period timer elapses, an external device to transmit an unlimited data steam through the circuit using the input external data input bus to enter the data.

9. A phase encoded transponder circuit for use in a passive transponder for the transmission of identification and other data from the transponder to an interrogating unit comprising

a memory containing data including a previously loaded identification code, at least one data word enable flags, and an external data flag;

a data bus connected to receive data from the memory;

timing circuitry connected to address the memory to access the data therein and to cause the data in the memory to be transferred from the memory to the data bus in a series of words in parallel;

parallel to serial data and phase conversion means connected to the data bus to convert the parallel words on the data bus into a serial phase encoded data stream;

at least one word enable latch connected to the data bus to test for the presence of the data word enable flag on the data bus;

a parallel input data bus connected to the data bus to be able to accept input data from an external source and present it on the data bus;

a latch connected to the data bus for testing for the presence of the external data flag; and

gating means connected for operating the parallel input data bus only when the word enable latch has been activated by the data word enable flag;

the gating means being further connected to the latch testing for the external data flag so that if the flag is set, the external parallel input bus is enabled to accept input data and if the flag is not set, data is read only from the memory, so that all data on the data bus may be converted by the parallel to serial conversion means into a common serial data stream wherein the transponder normally transmits up to an eight word message, the first word containing bits designated as the word enable flags.

10. A phase encoded transponder circuit as claimed in claim 9 wherein there are three word enable flags corresponding to the fifth, sixth and seventh words of the eight word message.

11. A phase encoded transponder circuit as claimed in claim 9 wherein there is also an exclusive-0R generating circuit connected to the data bus for performing an exclusive-OR function on the combined first seven words, the output of the exclusive-OR being presented on the data bus and transmitted as the last word in the eight word message.

12. A phase encoded transponder circuit as claimed in claim 9 wherein the identification code is contained in the first four words of the message, and wherein the external data flag is a bit in one of those first four words.

13. A phase encoded transponder circuit for use in a passive transponder for the transmission of identification and other data from the transponder to an interrogating unit comprising

a memory containing data including a previously loaded identification code, more than one data word enable flags, and an external data flag;

a data bus connected to receive data from the memory;

timing circuitry connected to address the memory to access the data therein and to cause the data in the memory to be transferred from the memory to the data bus in a series of words in parallel;

parallel to serial data and phase conversion means connected to the data bus to convert the parallel words on the data bus into a serial phase encoded data stream;

more than one word enable latch connected to the data bus to test for the presence of the data word enable flag on the data bus;

a priority encoder connected to the word enable latches to generate an address therefrom which may be accessed by an external device to select the external data words for presentation on the external data bus;

a parallel input data bus connected to the data bus to be able to accept input data from an external source and present it on the data bus;

a latch connected to the data bus for testing for the presence of the external data flag; and

gating means connected for operating the parallel input data bus only when the word enable latch has been activated by the data word enable flag;

the gating means being further connected to the latch testing for the external data flag so that if the flag is set, the external parallel input bus is enabled to accept input data and if the flag is not set, data is read only from the memory, so that all data on the data bus may be converted by the parallel to serial conversion means into a common serial data stream.

14. A method of operating a transponder for the transmission of identification information and also for enabling the optional transmission in the same transponder of optional external data comprising the steps of

providing a transponder including:

a memory portion including a fixed identification code and more than one word enable flag;

a data bus connected to receive data from the memory portion;

a parallel to serial and phase encoding circuit connected to convert parallel data on the data bus to a phase encoded serial data stream;

timing circuitry connected to control the operation of the parallel to serial and phase encoding circuit; and

at least one word enable latch connected to the data bus to test for the word enable flag is present on the bus to determine if the optional external data transmission is to be performed;

commencing a data message by the entry of information from the memory onto the data bus;

checking the flag in the identification code, and if it is set, setting the appropriate word enable latch;

if no word enable latch is set, at the termination of the transmission of the identification code, recommencing the transmission of the identification code;

if one word enable latch is set, at the termination of the transmission of the identification code, enabling a parallel input data bus which data is then converted and encoded in the same fashion as the identification code, and then recommencing the transmission of the identification code; and

if more than one word enable flag is set, prioritizing among the word enable latches and using the prioritizing data to create an address bus so that multiple words of external data may be transmitted.

15. A method of operating a transponder for the transmission of identification information and also for enabling the optional transmission in the same transponder of optional external data comprising the steps of

providing a transponder including:

a memory portion including a fixed identification code and more than one word enable flags imbedded in the first word of data;

a data bus connected to receive data from the memory portion, a parallel to serial and phase encoding circuit connected to convert parallel data on the data bus to a phase encoded serial data stream;

timing circuitry connected to control the operation of the parallel to serial and phase encoding circuit; and

at least one word enable latch connected to the data bus to test for the word enable flag is present on the bus to determine if the optional external data transmission is to be performed;

commencing a data message by the entry of information from the memory onto the data bus;

checking the flag in the identification code, and if it is set, setting the appropriate word enable latch;

if no word enable latch is set, at the termination of the transmission of the identification code, recommencing the transmission of the identification code; and

if one word enable latch is set, at the termination of the transmission of the identification code, enabling a parallel input data bus which data is then converted an decoded in the same fashion as the identification code, and then recommencing the transmission of the identification code.

16. A method of phase encoding a serial data stream consisting of data bits which are either true or false for transmission of coded identification information on a carrier from a phase encoded transponder comprising the steps of

transmitting a start bit of the data stream comprising a square wave of the carrier, the period of the square wave of the start bit selected to include two complete square waves in one single bit time;

at the commencement of each subsequent bit time, transmitting the carrier;

if the bit for the bit time is true, maintaining the carrier for substantially three-quarters of the bit time, after which the carrier transmission is ceased for the remaining one-quarter of the bit time;

if the bit for the bit time is false, maintaining the carrier for substantially one-quarter of the bit time after which the carrier transmission is ceased for the remaining three-quarters of the bit time.