Merged bipolar and insulated gate transistors
First Claim
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1. A plurality of merged vertical transistors and sidewall insulated gate transistor structures formed on a common substrate comprising:
- (a) a plurality of vertical transistors structures formed over an isolation region, which region is vertically and laterally electrically isolated from other portions of the common substrate and having at least;
(i) a vertical transistor collector layer extending in a plane and formed of a first type conductivity semiconductor material;
(ii) a vertical transistor base region formed of opposite type conductivity semiconductor material over said collector layer, said base region comprising an upper surface and a lower surface with sidewalls extending from said upper surface to said lower surface at an angle to said plane and wherein said collector layer is removed where one of said sidewalls intersects said plane to form a first mesa-like structure and expose a semiconductor junction at the intersection;
(iii) an emitter region formed in said base region; and
(b) an insulated gate transistor formed in and along one of said sidewalls and wherein the insulated gate transistor comprises a gate insulator formed on said sidewall and extending over said base region, a gate electrode formed on said gate insulator, a source region formed in said base region and extending laterally along said base region and a drain region formed in said collector layer.
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Abstract
A vertical bipolar transistor is formed along with an IGFET transistor in a process in which the bipolar transistor collector, base and emitter structure is formed in the body of a semiconductor mesa-like structure while the IGFET transistor is formed in and along one of the sidewalls of the structure. Source and drain regions are formed in the structure by ion-implantation using a polysilicon gate electrode formed over a gate insulator on the sidewall as a self-aligning mask.
133 Citations
22 Claims
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1. A plurality of merged vertical transistors and sidewall insulated gate transistor structures formed on a common substrate comprising:
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(a) a plurality of vertical transistors structures formed over an isolation region, which region is vertically and laterally electrically isolated from other portions of the common substrate and having at least; (i) a vertical transistor collector layer extending in a plane and formed of a first type conductivity semiconductor material; (ii) a vertical transistor base region formed of opposite type conductivity semiconductor material over said collector layer, said base region comprising an upper surface and a lower surface with sidewalls extending from said upper surface to said lower surface at an angle to said plane and wherein said collector layer is removed where one of said sidewalls intersects said plane to form a first mesa-like structure and expose a semiconductor junction at the intersection; (iii) an emitter region formed in said base region; and (b) an insulated gate transistor formed in and along one of said sidewalls and wherein the insulated gate transistor comprises a gate insulator formed on said sidewall and extending over said base region, a gate electrode formed on said gate insulator, a source region formed in said base region and extending laterally along said base region and a drain region formed in said collector layer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A merged vertical transistor and insulated gate transistor device comprising:
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(a) first mesa-like semiconductor structure formed over a substrate and laterally and electrically vertically isolated therefrom;
said structure having a top surface extending in a plane with sidewalls extending outwardly and downwardly from a central line passing orthogonally through the plane to intersect with said substrate;(b) a semiconductor p/n junction extending to said sidewalls in a plane parallel with said top surface; (c) a vertical transistor formed in said structure comprising; (i) a collector region at the bottom of said structure; (ii) a base region over said collector region forming said p/n junction with said collector region; (iii) and an emitter region in said base region; and (d) a first transistor formed in and along one of said sidewalls comprising; (i) a gate insulator extending along said sidewall and over said base region; (ii) a gate electrode over said insulator; (iii) a source region formed in said base region; and (iv) a drain region formed in said collector region. - View Dependent Claims (14, 15, 16, 17, 18, 19, 22)
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20. A merged vertical transistor and insulated gate transistor device comprising:
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(a) a first mesa-like semiconductor structure formed over a substrate and laterally and vertically electrically isolated therefrom;
said structure having a top surface extending in a plane with sidewalls extending outwardly and downwardly from a central line passing orthogonal through the plane to intersect with said substrate;(b) a semiconductor p/n junction extending to said sidewalls in a plane parallel with said top surface; (c) a vertical transistor formed in said structure comprising; (i) a collector region at the bottom of said structure; (ii) a base region over said collector region forming said p/n junction with said collector region; (iii) and an emitter region in said base region; and (d) a first transistor formed in and along one of said sidewalls comprising; (i) a gate insulator extending along said sidewall; (ii) a gate electrode over said insulator; (iii) a source region formed in said base region and extending laterally up to, but not underlying, said gate insulator; and (iv) a drain region formed in said base region. - View Dependent Claims (21)
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Specification