Bus adapter unit for digital processing system

• US 5,029,074 A
• Filed: 01/23/1990
• Issued: 07/02/1991
• Est. Priority Date: 06/29/1987
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Lipcon, Jesse, Maskas, Barry
• Primary Examiner(s): Harkcom, Gary V.
• Assistant Examiner(s): Jaffe, Michael A.
• Application Number:
  US07/474,202
• Time in Patent Office: 525 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/306
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A digital data processing system includes a plurality of processing subsystems, each including an adapter for enabling transfers between the resident subsystem and other subsystems. The adapter includes a master section which enables transfers of data initiated by the subsystem between the input/output bus and the higher level communications mechanism, a slave section which enables transfers of data between the higher level communications mechanism and the input/output bus initiated by another subsystem and an interprocessor communications mechanism for enabling the subsystem and other subsystems to communicate to thereby enable the other subsystems to perform control operations in connection with the subsystem.

Claims

1. An adapter comprising:

A. a transfer arrangement for performing transfers of information items between a system bus and a local bus, an information item including a data item and having an address on the system bus and an address on the local bus that is possibly different from said system bus address; and

B. a transfer control portion including;

i. a cache memory for caching address translation information for use during translation between the system bus address of an information item and the local bus address of said information item;

ii. an address translation portion for performing translations between said system bus addresses and said local bus addresses of information items transferred between said system bus and said local bus by said transfer arrangement, said address translation portion accessing said cache memory in performing at least some of said address translations; and

iii. a control arrangement for controlling transfers by said transfer arrangement, said control arrangement enabling said transfer translation portion to perform said translations.

2. An adapter as defined in claim 1 in which said transfer control portion further includes a fetch portion, responsive to the cache memory indicating that it is not currently caching address translation information for an address, for initiating a fetch operation over said local bus to retrieve address translation information for use by said address translation portion, said cache memory caching the address translation information as it is retrieved.

3. An adapter as defined in claim 1 wherein:

A. said transfer arrangement includes;

i. a master transfer path for performing transfers of said information items between said local bus and said system bus that are initiated over said local bus; and

ii. a slave transfer path for performing transfers of said information items between said local bus and said system bus that are initiated over said system bus;

B. said transfer control portion further including a master control portion for controlling said master transfer path and a slave transfer portion for controlling said slave transfer path, said master control portion further controlling said slave transfer path.

4. An adapter as defined in claim 3 wherein:

A. said master transfer path includes;

i. an address decode portion for receiving address information from said master transfer path;

ii. a data buffer for storing data;

B. said master transfer control portion for enabling said address decode portion to receive address information from said master transfer path originating from said local bus, and for enabling said data buffer to store data, said master transfer control portion enabling said address translation portion to perform a translation operation to translate an address received by said address decode portion for use in initiating a transfer over said system bus.

5. An adapter as defined in claim 4 wherein said slave transfer path includes:

A. a write buffer system for storing information from said system bus for transfer over said local bus;

B. a read buffer for storing information from said local bus for transfer over said system bus; and

C. said transfer control portion includes a slave transfer control portion for controlling storage of information within said write buffer system and said read buffer system.

6. An adapter as defined in claim 5 in which said write buffer system includes two buffers, said transfer control portion selectively enabling each buffer to store information received from said system bus.

7. An adapter as defined in claim 1 wherein said transfer control portion further includes an arbiter for controlling information transfers by said slave transfer path and said master transfer path over said system bus in response to selected conditions over said system bus.

8. A digital data processing system comprising:

A. a local bus for transferring local information items, a local information item including a local address;

B. a central processing unit for initiating transfers of local information items over said local bus;

C. a local memory responsive to transfers of local information items over said local bus;

D. a system bus for transferring system information items, a system information item including a system address;

E. an adapter comprising;

i. a transfer arrangement, including a slave transfer path for receiving system information items from said system bus and in response thereto initiating transfers of local information items over said local bus, the local address of a local information item initiated in response to a system information item possibly being different from the system address of said system information item,

ii. a transfer control portion including;

a. a cache memory for caching address translation information for use during said transfers of said local information items over said local bus in response to said received system information items;

b. an address translation portion for performing a translation between the system address of a system information item and the local address of the local information item transferred over said local bus in response to said system information item by said transfer arrangement, said address translation portion accessing said cache memory in performing said address translation; and

c. a control arrangement for controlling transfers by said transfer arrangement, said control arrangement enabling said address translation portion to perform said translation.

9. A system as defined in claim 8 in which the local information item includes a local address and a local data item.

10. A system as defined in claim 8 in which the system information item includes a system address and a system data item.

11. A system as defined in claim 8 in which said transfer control portion further includes a fetch portion, responsive to the cache memory indicating that it is not currently caching address translation information for an address, for initiating a fetch operation over said local bus to retrieve address translation information for use by said address translation portion, said cache memory caching the address translation information as it is retrieved.

12. A system as defined in claim 8 wherein:

A. said transfer arrangement includes a master transfer path for receiving local information items from said local bus and in response thereto transmitting system information items over said system bus;

B. said transfer control portion further including a master control portion for controlling said master transfer path and a slave transfer portion for controlling said slave transfer path, said master control portion further controlling said slave transfer path.

13. A system as defined in claim 12 wherein:

A. said master transfer path includes;

i. an address decode portion for receiving address information from said master transfer path,

ii. a data buffer for storing data;

B. said master transfer control portion for enabling said address decode portion to receive address information from said master transfer path originating from said local bus, and for enabling said data buffer to store data, said master transfer control portion enabling said address translation portion to perform a translation operation to translate an address received by said address decode portion for use in initiating a transfer over said system bus.

14. A system as defined in claim 12 wherein said slave transfer path includes:

A. a write buffer system for storing information from said system bus for transfer over said local bus;

B. a read buffer for storing information from said local bus for transfer over said system bus; and

C. said transfer control portion includes a slave transfer control portion for controlling storage of information within said write buffer system and said read buffer system.

15. A system as defined in claim 14 in which said write buffer system includes two buffers, said transfer control portion selectively enabling said buffer to store information received from said system bus.

16. A system as defined in claim 8 wherein said transfer control portion further includes an arbiter for controlling information transfers by said slave transfer path and said master transfer path over said system bus in response to selected conditions over said system bus.

17. A digital data processing system comprising:

A. a system bus for transferring system information items, a system information item including a system address;

B. a digital data processing subsystem for initiating transfers of system information items over said system bus;

C. a local bus for transferring local information items, a local information item including a local address;

D. an adapter comprising;

i. a transfer arrangement, including a slave transfer path for receiving system information items from said system bus and in response thereto initiating transfers of local information items over said local bus, the local address of a local information item initiated in response to a system information item possibly being different from the system address of said system information item,

ii. a transfer control portion including;

a. a cache memory for caching address translation information for use during said transfers of said local information items over said local bus in response to said received system information items;

b. an address translation portion for performing a translation between the system address of a system information item and the local address of the local information item transferred over said local bus in response to said system information item by said transfer arrangement, said address translation portion accessing said cache memory in performing said address translation; and

c. a control arrangement for controlling transfers by said transfer arrangement, said control arrangement enabling said address translation portion to perform said translation.

18. A system as defined in claim 17 in which the local information item includes a local address and a local data item.

19. A system as defined in claim 17 in which the system information item includes a system address and a system data item.

20. A system as defined in claim 17 in which said transfer control portion further includes a fetch portion, responsive to the cache memory indicating that it is not currently caching address translation information for an address, for initiating a fetch operation over said local bus to retrieve address translation information for use by said address translation portion, said cache memory caching the address translation information as it is retrieved.

21. A system as defined in claim 17 wherein:

A. said transfer arrangement includes a master transfer path for receiving local information items from said local bus and in response thereto transmitting system information items over said system bus;

B. said transfer control portion further including a master control portion for controlling said master transfer path and a slave transfer portion for controlling said slave transfer path, said master control portion further controlling said slave transfer path.

22. A system as defined in claim 21 wherein:

A. said master transfer path includes;

i. an address decode portion for receiving address information from said master transfer path,

ii. a data buffer for storing data;

B. said master transfer control portion for enabling said address decode portion to receive address information from said master transfer path originating from said local bus, and for enabling said data buffer to store data, said master transfer control portion enabling said address translation portion to perform a translation operation to translate an address received by said address decode portion for use in initiating a transfer over said system bus.

23. A system as defined in claim 21 wherein said slave transfer path includes:

A. a write buffer system for storing information from said system bus for transfer over said local bus;

B. a read buffer for storing information from said local bus for transfer over said system bus; and

C. said transfer control portion includes a slave transfer control portion for controlling storage of information within said write buffer system and said read buffer system.

24. A system as defined in claim 23 in which said writer buffer system includes two buffers, said transfer control portion selectively enabling each buffer to store information received from said system bus.

25. A system as defined in claim 17 wherein said transfer control portion further includes an arbiter for controlling information transfers by said slave transfer path and said master transfer path over said system bus in response to selected conditions over said system bus.

34. A system as defined in claim 23 wherein said transfer control portion further includes an arbiter for controlling information transfers by said slave transfer path and said master transfer path over said system bus in response to selected conditions over said system bus.

26. A digital data processing system comprising:

A. a system bus for transferring system information items, a system information item including a system address;

B. a plurality of digital data processing subsystems for initiating transfers of system information items over said system bus, said digital data processing subsystems each comprising;

i. a local bus for transferring local information items, a local information item including a local address;

ii. a central processing unit for initiating transfers of local information items over said local bus;

iii. a local memory responsive to transfers of local information items over said local bus;

iv. an adapter comprising;

a. a transfer arrangement, including a slave transfer path for receiving system information items from said system bus and in response thereto initiating transfers of local information items over said local bus, the local address of a local information item initiated in response to a system information item possibly being different from the system address of said system information item,

b. a transfer control portion including;

I. a cache memory for caching address translation information for use during said transfers of said local information items over said local bus in response to said received system information items;

II. an address translation portion for performing a translation between the system address of a system information item and the local bus in response to said system information item by said transfer arrangement, said address translation portion accessing said cache memory in performing said address translation; and

III. a control arrangement for controlling transfers by said transfer arrangement, said control arrangement enabling said address translation portion to perform said translation.

27. A system as defined in claim 26 in which the local information item includes a local address and a local data item.

28. A system as defined in claim 26 in which the system information item includes a system address and a system data item.

29. A system as defined in claim 26 in which said transfer control portion further includes a fetch portion, responsive to the cache memory indicating that it is not currently caching address translation information for an address, for initiating a fetch operation over said local bus to retrieve address translation information for use by said address translation portion, said cache memory caching the address translation information as it is retrieved.

30. A system as defined in claim 26 wherein:

A. said transfer arrangement includes a master transfer path for receiving local information items from said local bus and in response thereto transmitting system information items over said system bus;

B. said transfer control portion further including a master control portion for controlling said master transfer path and a slave transfer portion for controlling said slave transfer path, said master control portion further controlling said slave transfer path.

31. A system as defined in claim 30 wherein:

A. said master transfer path includes;

i. an address decode portion for receiving address information from said master transfer path,

ii. a data buffer for storing data;

B. said master transfer control portion for enabling said address decode portion to receive address information from said master transfer path originating from said local bus, and for enabling said data buffer to store data, said master transfer control portion enabling said address translation portion to perform a translation operation to translate an address received by said address decode portion for use in initiating a transfer over said system bus.

32. A system as defined in claim 30 wherein said slave transfer path includes:

A. a write buffer system for storing information from said system bus for transfer over said local bus;

B. a read buffer for storing information from said local bus for transfer over said system bus; and

C. said transfer control portion includes a slave transfer control portion for controlling storage of information within said write buffer system and said read buffer system.

33. A system as defined in claim 32 in which said write buffer system includes two buffers, said transfer control portion selectively enabling each buffer to store information received from said system bus.