Method and apparatus for providing high speed parallel transfer of bursts of data

• US 5,029,124 A
• Filed: 05/17/1988
• Issued: 07/02/1991
• Est. Priority Date: 05/17/1988
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Sills, Kenneth D., Leahy, James N.
• Primary Examiner(s): Moffitt, James W.
• Assistant Examiner(s): Rudolph, Rebecca L.
• Application Number:
  US07/195,049
• Time in Patent Office: 1,141 Days
• Field of Search: 364/200 MS, 364/900 MS, 371/32, 371/33, 370/85.1, 370/85.2, 370/85.3, 370/85.4, 370/85.5, 370/85.11
• US Class Current: 710/105
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence

Abstract

Method and apparatus for high speed parallel transfer of bursts of data between a device and an external interface bus. A burst mode asynchronous protocol is utilized, in which synchronous bursts of data using DATA VALID signals are followed by an asynchronous handshake using an ACKNOWLEDGE signal. The apparatus includes a burst register for storing and transmitting the data words in a burst, and control logic responsive to DATA VALID and ACKNOWLEDGE signals and providing control signals to operate the burst register.

Claims

1. A device for providing high speed parallel transfer of bursts of data between the device and an external interface bus, each burst including a predetermined number of data bits in a fixed number of multibit data words, the external interface bus including a plurality of data lines, with each data line corresponding to one bit in a data word being transferred, and the external interface bus also including a first and second synchronizing line carrying ACKNOWLEDGE and DATA VALID signals, and a direction line, the device comprising:

transfer means for coupling the device to the external interface bus to transmit and receive signals on the data lines, synchronizing lines, and direction line;

burst register means coupled to the transfer means, including a plurality of storage elements equal to the predetermined number, for transmitting a single multibit data word from the storage elements to the data lines in response to a first control signal, and for storing a single multibit data word in the storage elements from the data lines in response to a second control signal; and

control means coupled to the transfer means and the burst register means,

for providing a DIRECTION OUT signal to the transfer means for output to the direction line to enable transmission of a burst of data to the data lines, for sequentially providing a plurality of first control signals equal to the fixed number to the burst register means to sequentially transmit each data word of the burst from the burst register means to the transfer means, and for sequentially providing a plurality of DATA VALID signals equal to the fixed number to the transfer means for output to one of the synchronizing lines, each DATA VALID signal being provided to the transfer means after a corresponding data word in the burst is sequentially transmitted from the burst register means, to enable synchronous reception of each data word in the burst, the control means monitoring the other synchronizing line and being responsive to assertion of an ACKNOWLEDGE signal on the other synchronizing line prior to transmission of the burst to prevent a first data word in the burst from being transmitted from the burst register means until after the ACKNOWLEDGE signal is deasserted; and

the control means being responsive to assertion of a DIRECTION IN signal on the direction line to enable storage of a burst from the data lines, for monitoring one of the synchronizing lines, for sequentially providing a plurality of second control signals equal to the fixed number to the burst register means, each second control signal being provided to the burst register means in response to assertion of a corresponding DATA VALID signal on the one synchronizing line to sequentially store each data word of the burst in the burst register means, for asserting a single ACKNOWLEDGE signal on the other synchronizing line after receiving a DATA VALID signal corresponding to a first data word in the burst, and for deasserting the ACKNOWLEDGE signal on the other synchronizing line after the predetermined number of storage elements in the burst register means are ready to store another burst of data.

2. A device in accordance with claim 1, in which the burst register means comprises a FIFO register means for transmitting and storing the fixed number of multibit data words.

3. A device in accordance with claim 2, in which the FIFO register means reads out a single multibit data word to the transfer means in response to the coupling of each first control signal to the FIFO register means, and the FIFO register means writes in a single multibit data word from the transfer means in response to the coupling of each second control signal to the FIFO register means.

4. A device in accordance with claim 2, in which the FIFO register means shifts out a single multibit data word to the transfer means in response to the coupling of each first control signal to the FIFO register means, and the FIFO register means shifts in a single multibit data word from the transfer means in response to the coupling of each second control signal to the FIFO register means.

5. A device in accordance with claim 4, in which the control means comprises a state sequencer.

6. A device in accordance with claim 4, in which the device comprises a controller for a storage device.

7. A device in accordance with claim 1, in which the control means comprises a state sequencer.

8. A device in accordance with claim 1, in which the device comprises a controller for a storage device.

9. A device in accordance with claim 1, and further comprising mode selection means for designating a selected operating mode for the device.

10. A device in accordance with claim 1, and further comprising:

an internal bus including a second plurality of data lines coupled to the burst register means and the control means;

a local memory coupled to the internal bus; and

a processor coupled to the internal bus.

11. A device in accordance with claim 1, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst of data by a word, count value of zero.

12. A device in accordance with claim 1, in which the control means further comprises mode register means for storing a bit that indicates whether the device is in a data transmission mode or a data reception mode.

13. A device in accordance with claim 12, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst by a word count value of zero.

14. A device in accordance with claim 1, in which the external interface bus includes a burst enable line, and the control means monitors the burst enable line and provides only a single first control signal to the burst register means during a data transfer from the device, at times when a BURST ENABLE signal is not asserted, to prevent transmission of more than one multibit data word from the device until after a corresponding ACKNOWLEDGE signal is asserted and deasserted on the other synchronizing line.

15. A device in accordance with claim 14, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst by a word count value of zero.

16. A device in accordance with claim 14, in which the external interface bus includes a burst done line, and the control means provides a BURST DONE signal to the transfer means for output to the burst done line at times when a last data word in a partial burst is transmitted from the burst register means, and the control means monitors the burst done line and is responsive to the assertion of a BURST DONE signal to identify to the burst register means a last data word at times when a partial burst is transferred to the device.

17. A device in accordance with claim 16, in which the external interface bus further includes a parity line carrying a parity bit to indicate the parity of a multibit data word on the data lines, wherein:

the transfer means transmits and receives parity bits on the parity line; and

the burst register means includes a plurality of parity storage elements for transmitting and storing parity bits corresponding to single multibit data words being transmitted and stored.

18. A device in accordance with claim 17, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst by a word count value of zero.

19. A device in accordance with claim 16, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst by a word count value of zero.

20. A device in accordance with claim 1, in which the external interface bus includes a burst done line, and the control means provides a BURST DONE signal to the transfer means for output to the burst done line at times when a last data word in a partial burst is transmitted from the burst register means, and the control means monitors the burst done line and is responsive to the assertion of a BURST DONE signal to identify to the burst register means a last data word at times when a partial burst is transferred to the device.

21. A device in accordance with claim 20, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst by a word count value of zero.

22. A device in accordance with claim 20, in which the external interface bus further includes a parity line carrying a parity bit to indicate the parity of a multibit data word on the data lines, wherein:

the transfer means transmits and receives parity bits on the parity line; and

the burst register means includes a plurality of parity storage elements for transmitting and storing parity bits corresponding to single multibit data words being transmitted and stored.

23. A device in accordance with claim 22, in which the device comprises a controller for a storage device.

24. A device in accordance with claim 23, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst by a word count value of zero.

25. A device in accordance with claim 22, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst by a word count value of zero.

26. A device in accordance with claim 1, in which the external interface bus further includes a parity line carrying a parity bit to indicate the parity of a multibit data word on the data lines, wherein:

the transfer means transmits and receives parity bits on the parity line; and

the burst register means includes a plurality of parity storage elements for transmitting and storing parity bits corresponding to single multibit data words being transmitted and stored.

27. A device in accordance with claim 26, in which:

the control means further comprises parity error status register means for storing a bit that indicates whether the device has detected a parity error in a data word received by the device; and

the device further comprises parity check means, coupled to the transfer means and the control means, for monitoring the received data bits and parity bits, and for setting the bit in the parity error status register means in response to the detection of a parity error in the received data word.

28. A device in accordance with claim 27, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst by a word count value of zero.

29. A device in accordance with claim 26, in which the control means further comprises word count register means for storing the fixed number as a word count prior to transfer of a burst, and the control means decrements the word count in the word count register means in response to the assertion of a DATA VALID signal, wherein the word count register means indicates completion of transfer of a burst by a word count value of zero.

30. A process for providing high speed parallel transfer of bursts of data via an external interface bus between a first device and a second device, each burst including a predetermined number of data bits in a fixed number of multibit data words, each device including a plurality of storage elements equal in number to the predetermined number for storing each burst of data, and the external interface bus including a first and second synchronizing line carrying ACKNOWLEDGE and DATA VALID signals, a direction line for control of data transfer, and a plurality of data lines each corresponding to one bit in a data word being transferred, the process comprising the steps of:

transmitting a DIRECTION OUT signal from the first device to the second device on the direction line;

monitoring the second synchronizing line by the first device to determine whether an ACKNOWLEDGE signal is being asserted by the second device;

sequentially transmitting a plurality of data words equal to the fixed number in a burst from the storage elements in the first device to the data lines, with the first data word in the burst not being transmitted at times when an ACKNOWLEDGE signal is being asserted by the second device;

sequentially transmitting a plurality of DATA VALID signals equal to the fixed number from the first device to the first synchronizing line, each DATA VALID signal being transmitted after transmission of a corresponding data word in the burst and prior to transmission of a subsequent data word in the burst;

monitoring the first synchronizing line by the second device to determine whether a DATA VALID signal is being transmitted by the first device;

sequentially storing each data word in the burst into the storage elements in the second device at times when a DATA VALID signal is being transmitted by the first device;

asserting a single ACKNOWLEDGE signal by the second device on the second synchronizing line after a DATA VALID signal is transmitted from the first device corresponding to the first data word in the burst; and

deasserting the single ACKNOWLEDGE signal by the second device after the predetermined number of storage elements in the second device are ready to store another burst of data.

31. A process for providing high speed parallel transfer of a partial burst of data via an external interface bus between a first device and a second device, wherein a burst includes a predetermined number of data bits in a fixed number of multibit data words, and wherein each device includes a plurality of storage elements equal in number to the predetermined number for storing a burst of data, and the external interface bus includes a first and second synchronizing line carrying ACKNOWLEDGE and DATA VALID signals, a direction line for control of data transfer, a burst done line, and a plurality of data lines each corresponding to one bit in a data word being transferred, the process comprising the steps of:

transmitting a DIRECTION OUT signal from the first device to the second device on the direction line;

monitoring the second synchronizing line by the first device to determine whether an ACKNOWLEDGE signal is being asserted by the second device;

sequentially transmitting a plurality of data words equal to a number less than the fixed number in a partial burst from the storage elements in the first device to the data lines, with the first data word in the partial burst not being transmitted at times when an ACKNOWLEDGE signal is being asserted by the second device;

sequentially transmitting a plurality of DATA VALID signals equal to the number less than the fixed number from the first device to the first synchronizing line, each DATA VALID signal being transmitted after transmission of a corresponding data word in the partial burst and prior to transmission of a subsequent data word in the partial burst;

transmitting a BURST DONE signal from the first device to the second device on the burst done line at times when a last data word in the partial burst is transmitted from the storage elements in the first device to the data lines;

monitoring the first synchronizing line by the second device to determine whether a DATA VALID signal is being transmitted by the first device;

sequentially storing each data word in the partial burst into the storage elements in the second device at times when a DATA VALID signal is being transmitted by the first device;

asserting a single ACKNOWLEDGE signal by the second device on the second synchronizing line after a DATA VALID signal is transmitted from the first device corresponding to the first data word in the partial burst;

monitoring the burst done line by the second device to determine whether a BURST DONE signal is being transmitted by the first device; and

deasserting the single ACKNOWLEDGE signal by the second device after a BURST DONE signal is transmitted from the first device corresponding to the last data word in the partial burst and after the predetermined number of storage elements in the second device are ready to store a burst of data.

32. A process for providing high speed parallel transfer of bursts of data via an external interface bus between a first device and a second device, each burst including a predetermined number of data bits in a fixed number of multibit data words, each device including a plurality of storage elements equal in number to the predetermined number for storing each burst of data, and the external interface bus including a first and second synchronizing line carrying ACKNOWLEDGE and DATA VALID signals, a direction line for control of data transfer, and a plurality of data lines each corresponding to one bit in a data word being transferred, the process comprising the steps of:

transmitting a DIRECTION OUT signal from the first device to the second device on the direction line during a first transfer;

monitoring the second synchronizing line by the first device to determine whether an ACKNOWLEDGE signal is being asserted by the second device during the first transfer;

sequentially transmitting a plurality of data words equal to the fixed number in a burst from the storage elements in the first device to the data lines, with the first data word in the burst not being transmitted at times when an ACKNOWLEDGE signal is being asserted by the second device during the first transfer;

sequentially transmitting a plurality of DATA VALID signals equal to the fixed number from the first device to the first synchronizing line, each DATA VALID signal being transmitted after transmission of a corresponding data word in the burst and prior to transmission of a subsequent data word in the burst during the first transfer;

monitoring the first synchronizing line by the second device to determine whether a DATA VALID signal is being transmitted by the first device during the first transfer;

sequentially storing each data word in the burst into the storage elements in the second device at times when a DATA VALID signal is being transmitted by the first device during the first transfer;

asserting a single ACKNOWLEDGE signal by the second device on the second synchronizing line after a DATA VALID signal is transmitted from the first device corresponding to the first data word in the burst during the first transfer;

deasserting the single ACKNOWLEDGE signal by the second device after the predetermined number of storage elements in the second device are ready to store another burst of data during the first transfer;

transmitting a DIRECTION OUT signal from the second device to the first device on the direction line during a second transfer;

monitoring the first synchronizing line by the second device to determine whether an ACKNOWLEDGE signal is being asserted by the first device during the second transfer;

sequentially transmitting a plurality of data words equal to the fixed number in a burst from the storage elements in the second device to the data lines, with the first data word in the burst not being transmitted at times when an ACKNOWLEDGE signal is being asserted by the first device during the second transfer;

sequentially transmitting a plurality of DATA VALID signals equal to the fixed number from the second device to the second synchronizing line, each DATA VALID signal being transmitted after transmission of a corresponding data word in the burst and prior to transmission of a subsequent data word in the burst during the second transfer;

monitoring the second synchronizing line by the first device to determine whether a DATA VALID signal is being transmitted by the second device during the second transfer;

sequentially storing each data word in the burst into the storage elements in the first device at times when a DATA VALID signal is being transmitted by the second device during the second transfer;

asserting a single ACKNOWLEDGE signal by the first device on the first synchronizing line after a DATA VALID signal is transmitted from the second device corresponding to the first data word in the burst during the second transfer; and

deasserting the single ACKNOWLEDGE signal by the first device after the predetermined number of storage elements in the first device are ready to store another burst of data during the second transfer.

33. A process for providing high speed parallel transfer of a partial burst of data via an external interface bus between a first device and a second device, wherein a burst includes a predetermined number of data bits in a fixed number of multibit data words, and wherein each device includes a plurality of storage elements equal in number to the predetermined number for storing a burst of data, and the external interface bus includes a first and second synchronizing line carrying ACKNOWLEDGE and DATA VALID signals, a direction line for control of data transfer, a burst done line, and a plurality of data lines each corresponding to one bit in a data word being transferred, the process comprising the steps of:

transmitting a DIRECTION OUT signal from the first device to the second device on the direction line during a first transfer;

monitoring the second synchronizing line by the first device to determine whether an ACKNOWLEDGE signal is being asserted by the second device during the first transfer;

sequentially transmitting a plurality of data words equal to a number less than the fixed number in a partial burst from the storage elements in the first device to the data lines, with the first data word in the partial burst not being transmitted at times when an ACKNOWLEDGE signal is being asserted by the second device during the first transfer;

sequentially transmitting a plurality of DATA VALID signals equal to the number less than the fixed number from the fist device to the first synchronizing line, each DATA VALID signal being transmitted after transmission of a corresponding data word in the partial burst and prior to transmission of a subsequent data word in the partial burst during the first transfer;

transmitting a BURST DONE signal from the first device to the second device on the burst done line at times when a last data word in the partial burst is transmitted from the storage elements in the first device to the data lines during the first transfer;

monitoring the first synchronizing line by the second device to determine whether a DATA VALID signal is being transmitted by the first device during the first transfer;

sequentially storing each data word in the partial burst into the storage elements in the second device at times when a DATA VALID signal is being transmitted by the first device during the first transfer;

asserting a single ACKNOWLEDGE signal by the second device on the second synchronizing line after a DATA VALID signal is transmitted from the first device corresponding to the first data word in the partial burst during the first transfer;

monitoring the burst done line by the second device to determine whether a BURST DONE signal is being transmitted by the first device during the first transfer;

deasserting the single ACKNOWLEDGE signal by the second device after a BURST DONE signal is transmitted from the first device corresponding to the last data word in the partial burst and after the predetermined number of storage elements in the second device are ready to store a burst of data during the first transfer;

transmitting a DIRECTION OUT signal from the second device to the first device on the direction line during a second transfer;

monitoring the first synchronizing line by the second device to determine whether an ACKNOWLEDGE signal is being asserted by the first device during the second transfer;

sequentially transmitting a plurality of data words equal to a number less than the fixed number in a partial burst from the storage elements in the second device to the data lines, with the first data word in the partial burst not being transmitted at times when an ACKNOWLEDGE signal is being asserted by the first device during the second transfer;

sequentially transmitting a plurality of DATA VALID signals equal to the number less than the fixed number from the second device to the second synchronizing line, each DATA VALID signal being transmitted after transmission of a corresponding data word in the partial burst and prior to transmission of a subsequent data word in the partial burst during the second transfer;

transmitting a BURST DONE signal from the second device to the first device on the burst done line at times when a last data word in the partial burst is transmitted from the storage elements in the second device to the data lines during the second transfer;

monitoring the second synchronizing line by the first device to determine whether a DATA VALID signal is being transmitted by the second device during the second transfer;

sequentially storing each data word in the partial burst into the storage elements in the first device at times when a DATA VALID signal is being transmitted by the second device during the second transfer;

asserting a single ACKNOWLEDGE signal by the first device on the first synchronizing line after a DATA VALID signal is transmitted from the second device corresponding to the first data word in the partial burst during the second transfer;

monitoring the burst done line by the first device to determine whether a BURST DONE signal is being transmitted by the second device during the second transfer; and

deasserting the single ACKNOWLEDGE signal by the first device after a BURST DONE signal is transmitted from the second device corresponding to the last data word in the partial burst and after the predetermined number of storage elements in the first device are ready to store a burst of data during the second transfer.