Transceiver providing selectable frequencies and spreading sequences

• US 5,029,180 A
• Filed: 08/13/1990
• Issued: 07/02/1991
• Est. Priority Date: 03/23/1989
• Status: Expired due to Term

• Current Assignee: Echelon Systems Corp.
• Original Assignee: Echelon Systems Corp.
• Inventors: Cowart, Brooks E.
• Primary Examiner(s): Cangialosi, Salvatore
• Application Number:
  US07/567,232
• Time in Patent Office: 323 Days
• Field of Search: 375/1, 380/34
• US Class Current: 375/141
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/70755 Setting of lock conditions, e.g. threshold
• CPC Class Codes: H04B 1/70757 with increased resolution, i.e. higher than half a chip H04B1/70758 takes precedence
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates

Abstract

A transceiver for transmitting and receiving digital data is disclosed. The transceiver employs direct sequence spread spectrum communications techniques for reducing interference among multiple users in a communications network environment. Each transceiver has a transmitter for locking a digital bit stream to a predetermined spread spectrum chip sequence and carrier signal. Frequency of the carrier signal and the chip sequence. Both the carrier signal, the chip sequence and the bit stream rate are derived from an integrally related to an accurate reference frequency to facilitate rapid acquisition and decoding of the signal by another transceiver. To provide for multiple communications channels on a single transmission medium, means for producing selectable carrier frequencies and/or selectable spreading sequences are included. The transceiver also has a receiver portion for acquiring and decoding a transmitted and direct sequence spread spectrum signal to recover the digital bit stream using the spread spectrum chip sequence and carrier signal.

Claims

1. An integrated circuit for transmitting and receiving digital information across various communications media comprising:

a frequency means for generating a reference frequency;

transmitter means for locking a digital bit stream, a carrier signal and a pseudonoise chip sequence to produce a direct sequence spread spectrum signal for transmission to another integrated circuit;

said transmitter means including a circuit means for modifying said pseudonoise chip sequence to provide selectable carrier frequencies for multiple communications channels on a single transmission medium;

receiver means for acquiring and decoding a previously transmitted direct sequence spread spectrum signal using a local carrier signal and a local pseudonoise chip sequence to recover said digital bit stream;

wherein said carrier signal and said pseudonoise chip sequence are substantially identical to said local carrier signal and said local pseudonoise chip sequence, respectively, and each are derived from, and integral multiples of, said reference frequency.

2. The integrated circuit of claim 1 wherein said receiver further comprises an integrate and dump filter for demodulating said carrier signal from said direct sequence spread spectrum signal.

3. The integrated circuit of claim 2 wherein said circuit means comprises a means for modulating said digital bit stream with a selected chip sequence.

4. The integrated circuit of claim 3 further comprising a correlator means for correlating said demodulated direct sequence spread spectrum signal with all possible code positions of said local pseudonoise chip sequence to recover said digital bit stream.

5. The integrated circuit of claim 4 wherein said correlator means comprises at least one linear shift register.

6. The integrated circuit of claim 5 wherein said modulation means comprises:

a first register containing said selected chip sequence; and

logic means for loading said selected chip sequence from said first register to said at least one linear shift register such that as each data bit becomes available, said selected chip sequence is shifted sequentially through said at least one linear shift register and applied to the bit of said digital data stream for transmission.

7. The integrated circuit of claim 6 further comprising phase adjustment means for detecting and correcting phase errors between said direct sequence spread spectrum signal and said local carrier signal.

8. A transceiver for transmitting and receiving digital information across various communications media comprising:

a frequency means for generating a frequency;

transmitter means for locking a digital bit stream, a carrier signal and a pseudonoise chip sequence to produce a direct sequence spread spectrum signal for transmission to another transceiver;

said transmitter means including the circuit means for generating selectable carrier frequencies to provide for multiple communications channels on a single transmission medium;

receiver means for acquiring and decoding a previously transmitted direct sequence spread spectrum signal using a local carrier signal and local pseudonoise chip sequence to recover said digital bit stream;

wherein said carrier signal and said pseudonoise chip sequence are substantially identical to said local carrier signal and said local pseudonoise chip sequence, respectively, and each are derived, and integral multiples, of said reference frequency.

9. The transceiver of claim 8 wherein said receiver means further comprises an integrate and dump filter for demodulating said carrier signal from said direct sequence spread spectrum signal.

10. The transceiver of claim 8 wherein said circuit means includes a means for providing correction for the phase precession between said carrier signal and said local carrier signal.

11. The transceiver of claim 10 further comprising a correlator means for correlating said demodulated direct sequence spread spectrum signal with all possible code positions of said local pseudonoise chip sequence to recover said digital bit stream.