Voltage regulator circuit

• US 5,029,282 A
• Filed: 12/14/1989
• Issued: 07/02/1991
• Est. Priority Date: 02/16/1989
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ito, Makoto
• Primary Examiner(s): Miller, Stanley D.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US07/450,569
• Time in Patent Office: 565 Days
• Field of Search: 307/296.8, 307/296.7, 307/296.2, 307/296.1, 307/491, 307/494, 307/304
• US Class Current: 327/536
• CPC Class Codes: G05F 3/205 Substrate bias-voltage generators for static stores G11C5/146
• CPC Class Codes: G05F 3/24 wherein the transistors are of the field-effect type only G05F3/205, G05F3/26, G05F3/30 take precedence
• CPC Class Codes: G11C 16/30 Power supply circuits
• CPC Class Codes: G11C 5/145 Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor G11C5/141 takes precedence
• CPC Class Codes: G11C 5/147 Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops G11C5/141 takes precedence
• CPC Class Codes: H02M 3/073 Charge pumps of the Schenkel-type

Abstract

A voltage regulator circuit for use with an integrated circuit with a charge pump circuit having a voltage output terminal and a voltage input terminal in which a plurality of voltage regulating P-channel MOS transistors, each of which has its source and substrate connected together and its gate and drain connected together, are connected in series between the voltage output and input terminals of the charge pump circuit.

Claims

1. A voltage regulator circuit for use with a semiconductor integrated circuit having a charge pump circuit with a voltage output terminal and a voltage input terminal, including a plurality of P-channel MOS transistors connected in series between said voltage output terminal and said voltage input terminal of said charge pump circuit, each of said P-channel MOS transistors having its source and substrate connected together and its gate and drain connected together.

2. A voltage regulator circuit according to claim 1, in which between one end of the series connection of said P-channel MOS transistors and said voltage output terminal of said charge pump circuit is connected a P-channel MOS transistor which has its source and substrate connected together and is supplied at its gate with an enable signal synchronized with an enable signal for said charge pump circuit.

3. A voltage regulator circuit according to claim 1, in which between the other end of the series connection of said P-channel MOS transistors and said voltage input terminal of said charge pump circuit is connected a P-channel MOS transistor having its substrate, gate and drain connected together or a diode.

4. A voltage regulator circuit according to claim 2, in which a P-channel MOS transistor having its substrate, gate and drain connected together or a diode is connected between the other end of the series connection of said P-channel MOS transistors and said voltage input terminal of said charge pump circuit.

5. A voltage regulator circuit according to claim 1, in which said voltage regulator circuit regulates a boosted voltage to be applied to memory cells of a nonvolatile memory integrated circuit.

6. A voltage regulator circuit according to claim 2, in which said voltage regulator circuit regulates a boosted voltage to be applied to memory cells of a nonvolatile memory integrated circuit.

7. A voltage regulator circuit according to claim 3, in which said voltage regulator circuit regulates a boosted voltage to be applied to memory cells of a nonvolatile memory integrated circuit.

8. A voltage regulator circuit according to claim 4, in which said voltage regulator circuit regulates a boosted voltage to be applied to memory cells of a nonvolatile memory integrated circuit.