Spread spectrum signal demodulation circuit

• US 5,031,191 A
• Filed: 05/16/1990
• Issued: 07/09/1991
• Est. Priority Date: 05/17/1989
• Status: Expired due to Term

• Current Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Original Assignee: Sanyo Electric Company Limited (Panasonic Holdings Corporation)
• Inventors: Takagi, Hiroaki, Hiramatsu, Tatsuo
• Primary Examiner(s): Tarcza, Thomas H.
• Assistant Examiner(s): SWANN, TOD R
• Application Number:
  US07/524,102
• Time in Patent Office: 419 Days
• Field of Search: 375/1, 375/92, 375/111, 375/115, 380/46, 455/208, 455/209, 455/255, 455/257, 455/259, 455/265, 455/317
• US Class Current: 375/130
• CPC Class Codes: H04B 1/7075 with code phase acquisition

Abstract

A spread spectrum signal demodulation circuit includes a multiplier which multiplies an input spread spectrum signal by a demodulation PN code, and a demodulation PN code generator generates the demodulation PN code by utilizing an oscillation signal from a VCO as a clock signal thereof. An output of the multiplier is given to a bandpass filter and an output of which is integrated by an integration circuit. A first integrated value for a first time is compared with a second integrated value for a second time later than the first time and, in accordance with a comparison result, a frequency of the oscillation signal of the VCO is changed so that the demodulation PN code is synchronized with a modulation PN code included in the input spread spectrum signal.

Claims

1. A spread spectrum demodulation circuit, comprising:

a variable frequency oscillator a frequency of which is changed in accordance with a control signal as applied;

PN code generating means for generating a demodulation PN code by using an oscillation signal of said variable frequency oscillator as a clock thereof;

multiplying means for multiplying an input spread spectrum signal and said demodulation PN code;

filter means for receiving an output of said multiplying means;

first holding means for holding a first value associated with an output of said filter means at a first time;

second holding means for holding a second value associated with the output of said filter means at a second time later than said first time;

comparing means for comparing said first value and said second value being respectively held in said first holding means and said second holding means; and

controlling means for outputting said control signal in accordance with an output of said comparing means to control said variable frequency oscillator so that said demodulation PN code from said PN code generating means can be synchronized with a modulation PN code included in said input spread spectrum signal.

2. A spread spectrum signal demodulation circuit in accordance with claim 1, wherein said first holding means and said second holding means hold said first value and said second value obtained through sampling the output of said filter means at different times, respectively.

3. A spread spectrum demodulation circuit in accordance with claim 1, further comprising integration means for integrating the output of said filter means, wherein said first holding means and said second holding means hold said first value and said second value output from said integration means, respectively.

4. A spread spectrum signal demodulation circuit in accordance with claim 1, wherein said control means includes frequency changing means for changing the oscillation frequency of said variable frequency oscillator in a binary manner.

5. A spread spectrum signal demodulation circuit in accordance with claim 4, wherein said frequency changing means includes means for changing said oscillation frequency so that a frequency of said demodulation PN code and said oscillation frequency changed by said frequency changing means are almost equal.

6. A spread spectrum demodulation circuit in accordance with claim 1, wherein said PN code generating means includes means for generating a PN code having a reference phase, and means for outputting two synchronization PN codes respectively having a time difference between said PN code having a reference phase, said PN code having a reference phase being utilized as said demodulation PN code are almost equal.

7. A spread spectrum signal demodulation circuit in accordance with claim 6, wherein said multiplying means includes first multiplying means for multiplying said input spread spectrum signal by said PN code having a reference phase, and second multiplying means for multiplying said input spread spectrum signal by one of said synchronization PN codes, an output of said first multiplying means being output from an output terminal through filter means, and an output of said second multiplying means being input to said filter means.