Entry point mapping and skipping method and apparatus

• US 5,032,983 A
• Filed: 09/18/1989
• Issued: 07/16/1991
• Est. Priority Date: 04/10/1987
• Status: Expired due to Term

• Current Assignee: Tandem Computers Incorporated (HP Inc.)
• Original Assignee: Tandem Computers Incorporated (HP Inc.)
• Inventors: Lenoski, Daniel E., Fu, Peter L.
• Primary Examiner(s): Anderson, Lawrence E.
• Application Number:
  US07/409,978
• Time in Patent Office: 666 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/217
• CPC Class Codes: G06F 9/26 Address formation of the next micro-instruction G06F9/28 takes precedence; Microprogram storage or retrieval arrangements
• CPC Class Codes: G06F 9/261 Microinstruction address formation

Abstract

A fixed entry-point map to produce an entry point address of a first micro-instruction for a particular macro-instruction. That address is then incremented by a fixed number to produce the second, third, etc. micro-instructions for that macro-instruction. In a first embodiment, after a fixed number of these address skips, the addresses are incremented by 1 so that successive micro-instructions are in adjacent address locations. In a second embodiment, the number of skips is variable.

Claims

1. In a method for executing a macro-instruction with a series of microcode instructions stored in a microcode memory, an improved method for addressing the memory comprising the steps of:

(a) providing an entry point address of said microcode memory to an address register for said macroinstruction;

(b) repeatedly incrementing said address register by a first predetermined number (F) greater than one to provide an address of a next microcode instruction in said microcode memory, in a first, skipping mode such that microcode instructions for other macro-instructions are skipped over;

and incrementing said address register by one in a second, normal mode, such that addresses can be automatically incremented in both said first and second modes without reference to said microcode instructions for an increment amount

whereby to obtain the address of the next microinstruction during the execution of the macroinstruction the current address is first incremented by said first predetermined number and subsequently incremented by one without reference to the microinstructions.

2. The method of claim 1 wherein said second mode is entered upon the taking of a jump.

3. The method of claim 1 wherein said first, skipping mode continues while said address register contains an address in a first, fixed skipping address region.

4. The method of claim 3 wherein said first predetermined number is 512.

5. The method of claim 3 further comprising the step of storing a set of micro-instructions corresponding to a macro-instruction having said entry point address with a plurality of other sets of microcode instructions in a microcode instruction memory, each set of micro-instructions being selectable by a different macroinstruction such that the first microcode instruction in a first set of micro-instructions which has a first number of micro-instructions extending beyond said skipping address region is followed by said first number of first microinstructions of subsequent sets of micro-instructions that are fully contained up to the end of the set or up to a jump within the skipping address region.

6. In an apparatus for executing a macro-instruction with a series of microcode instructions in a microcode memory, an improved apparatus for addressing the microcode memory comprising:

an instruction register for holding said macroinstruction;

entry point table means, having an input coupled to an output of said instruction register and responsive to said macro-instruction, for providing an entry point address of said microcode memory at an output of said entry point table means for said macro-instruction;

first means, having an input coupled to said output of said entry point table means, for incrementing an address by a first predetermined number greater than one to provide an address of a next microcode instruction for said macro-instruction;

second means for incrementing an address by one; and

means for (a) coupling an output of said first means for incrementing to said microcode memory and to an input of said first means for incrementing in a first, skipping mode of operation and (b) coupling an output of said second means for incrementing to said microcode memory and to an input of said second means for incrementing in a second, normal mode of operation whereby to obtain the address of the next microinstruction during the execution of the macroinstruction the current address is first incremented by said first predetermined number and subsequently incremented by one without reference to the microinstructions.

7. The apparatus of claim 6 wherein said means for providing an entry point address is permanently fixed.

8. The apparatus of claim 6 wherein said first number is 512.

9. The apparatus of claim 6 wherein said first and second means for incrementing comprise a single counter having multiple carry inputs.

10. The apparatus of claim 6 wherein said means for coupling comprises a decode circuit responsive to a state bit indicating that said apparatus is in said skipping mode, said state bit being settable under micro-instruction control to produce a signal to select said first means for incrementing for said first, skipping mode and said second means for incrementing for said second, normal mode.

11. The apparatus of claim 6 wherein said means for coupling is controlled by a bit output of a micro program counter register which is set when a branch is taken, said bit output corresponding to a bit input, and further comprising a microcode instruction register having an output coupled to said bit input.

12. The apparatus of claim 11 wherein said bit output has a separate load enable, and further comprising a control register having an input coupled to said microcode instruction register and an output coupled to said load enable, such that the selection of the skipping or normal mode can be based on a branch in a micro-instruction.

13. In an apparatus for executing a macro-instruction with a series of microcode instructions in a microcode memory, an improved apparatus for addressing the microcode memory, comprising:

an instruction register for holding said macro-instruction;

entry point table means, having an input coupled to an output of said instruction register and responsive to said macro-instruction, for providing a fixed entry point address of said microcode memory at an output of said entry point table means for said macro-instruction;

first means, having an input coupled to said output of said entry point table means, for incrementing an address by a first predetermined number greater than one to provide an address of a next microcode instruction for said macro-instruction which skips over the addresses of intervening microcode instructions for other macroinstructions;

second means for incrementing an address by one;

a multiplexer having an input coupled to outputs of said first and second means for incrementing and an output coupled to said microcode memory and inputs of said first and second means for incrementing; and

a decode circuit having an input coupled to an output of said multiplexer and responsive to a portion of a current microcode memory address to produce an output select signal to a select input of said multiplexer to select said first means for incrementing when said current address is within a first, skipping block of addresses and said second means for incrementing when said current address is within a second block of addresses whereby to obtain the address of the next microinstruction during the execution of the macroinstruction the current address is first incremented by said first predetermined number and subsequently incremented by one without reference to the microinstructions.