Manufacturing ultra-thin wafer using a handle wafer

• US 5,034,343 A
• Filed: 03/08/1990
• Issued: 07/23/1991
• Est. Priority Date: 03/08/1990
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Rouse, George V., McLachlan, Craig J., Reinecke, Paul S.
• Primary Examiner(s): Chaudhuri, Olik
• Assistant Examiner(s): Horton, Kenneth
• Application Number:
  US07/490,316
• Time in Patent Office: 502 Days
• Field of Search: 437/62, 437/86, 437/974, 437/228, 148/DIG. 135
• US Class Current: 438/400
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 21/76251 using bonding techniques
• CPC Class Codes: Y10S 148/135 Removal of substrate

Abstract

A process including bonding a first device wafer to a handle wafer by an intermediate bonding oxide layer and thinning the device wafer to not greater than 7 mils. An epitaxial device layer of under 1 mil may be added. Device formation steps are performed on a first surface of the first device wafer. This is followed by removing the handle wafer to produce a resulting wafer having substantially the thickness of the first device layer. To produce a silicon on insulator (SOI), a third device wafer is bonded to the first surface of the first device wafer by the intermediate oxide layer and the third wafer is thinned to not greater than 40 microns. The first and third device wafers form the resulting SOI wafer.

Claims

1. A method of fabricating integrated circuits in ultra thin wafers comprising:

bonding a first device wafer to a handle wafer by an intermediate oxide layer and thinning said first device wafer to a desired wafer thickness of not greater than 7 mils;

performing device formation steps on a first surface of said thinned first device wafer; and

removing said handle wafer to produce a wafer having substantially the thickness of said first device wafer.

2. A method according to claim 1 including performing device isolation step after said bonding step and before said removing step.

3. A method according to claim 2, wherein:

said device isolation steps includes bonding a third device wafer to said first surface of said first device wafer by an intermediate oxide layer which forms part of said device isolation and thinning said third device wafer to no more than 40 microns and;

said device formation steps are performed on the surface of said third device wafer.

4. A method according to claim 3, wherein said device isolation step includes introducing impurities into said third device wafer to form lateral junction isolation.

5. A method according to claim 3, wherein said device isolation step includes etching said third device wafer to form lateral dielectric isolation.

6. A method according to claim 2, wherein said device isolation step includes introducing impurities into said first device wafer to form junction isolation.

7. A method according to claim 2, wherein said device isolation step includes etching said first device wafer to form lateral dielectric isolation.

8. A method according to claim 2, wherein said device isolation steps include implanting oxygen to form a dielectric layer within said first device wafer.

9. A method according to claim 1, wherein removing said handle wafer includes grinding said handle wafer for a substantial portion of its thickness and etching the remaining portion of said handle wafer using said oxide layer as an etching stop.

10. A method according to claim 1 including forming an expitaxial layer on said first device layer after thinning under 1 mil, and performing said device formation steps on said epitaxial layer.

11. A method according to claim 10

wherein said epitaxial layer is formed of a second conductivity type opposite a first conductivity type of said first device wafer to form horizontal junction isolation;

and

including etching said epitaxial layer down to said first device layer to form lateral dielectric isolation.

12. A method according to claim 10

wherein said epitaxial layer is formed of a second conductivity type opposite a first conductivity type of said first device wafer to form horizontal junction isolation;

and

including introducing impurities of said first conductivity type into said epitaxial layer to form lateral junction isolation extending down to said first device wafer.

13. A method of fabricating integrated circuits in ultra-thin wafers comprising:

bonding a first device wafer to a handle wafer by a first intermediate oxide layer and thinning said first device wafer to not greater than 7 mils;

bonding a third device wafer to said first device wafer by a second intermediate oxide layer and thinning the third wafer to less than 40 microns;

performing device formation steps on a first surface of said third device wafer; and

removing said handle wafer to produce a wafer having the thickness substantially of the combined first and third device wafers with device thickness defined by said third layer.

14. A method according to claim 13 including introducing impurities into said third device wafer to form lateral junction isolation before removing said handle wafer.

15. A method according to claim 13 including etching said third device wafer to form lateral dielectric isolation before removing said handle wafer.

16. A method according to claim 13, wherein removing said handle wafer includes grinding said handle wafer for a substantial portion of its thickness and etching the remaining portion of said handle wafer using said oxide layer as an etching stop.