Method of fabricating a bump electrode for an integrated circuit device

• US 5,034,345 A
• Filed: 08/01/1990
• Issued: 07/23/1991
• Est. Priority Date: 08/21/1989
• Status: Expired due to Term

• Current Assignee: Fuji Electric Systems Company Limited
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Shirahata, Hisashi
• Primary Examiner(s): Hearn, Brian E.
• Assistant Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US07/561,457
• Time in Patent Office: 356 Days
• Field of Search: 437/183, 437/187, 437/245, 437/189, 437/190, 437/192, 357/71
• US Class Current: 438/613
• CPC Class Codes: H01L 2224/05124 Aluminium [Al] as principal constituent
• CPC Class Codes: H01L 2224/05164 Palladium [Pd] as principal constituent
• CPC Class Codes: H01L 2224/05166 Titanium [Ti] as principal constituent
• CPC Class Codes: H01L 2224/05644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/10125 Reinforcing structures
• CPC Class Codes: H01L 2224/10126 Bump collar
• CPC Class Codes: H01L 2224/10145 Flow barriers
• CPC Class Codes: H01L 2224/1147 using a lift-off mask
• CPC Class Codes: H01L 2224/13006 Bump connector larger than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13007 Bump connector smaller than the underlying bonding area, e.g. than the under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/13016 in side view
• CPC Class Codes: H01L 2224/13019 at the bonding interface of the bump connector, i.e. on the surface of the bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 23/4822 Beam leads
• CPC Class Codes: H01L 24/03 Manufacturing methods
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/11 Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01022 : Titanium [Ti]
• CPC Class Codes: H01L 2924/01023 : Vanadium [V]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01046 : Palladium [Pd]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/14 : Integrated circuits

Abstract

A bump electrode for connecting a semiconductor device with an external lead is disclosed. The bump electrode is designed to eliminate mechanical stress caused by molten metal flowing onto the semiconductor chip during manufacture. The bump electrode metal is formed over an upper and lower foundation film. The lower foundation film extends out laterally beyond the upper foundation film and the bump electrode metal. The lower foundation film does not get wet with the flowing molten metal, and, therefore, prevents the molten metal from flowing onto the chip.

Claims

1. A bump electrode for connecting a semiconductor device to an external lead by melting a junction metal coating, comprising:

a semiconductor substrate containing the semiconductor device;

a conducting layer formed on the semiconductor substrate having first and second ends, the first end connected to the semiconductor device;

a protection layer formed over the conducting layer having an aperture toward the second end of the conducting layer;

a foundation layer of material which does not get wet by the junction metal coating formed on the protection layer over the aperture, the foundation layer in electrical contact with the conducting layer through the aperture;

a bump electrode metal formed on the foundation layer, a portion of the foundation layer extending laterally beyond the bump electrode metal,

whereby the junction metal coating cannot flow past the foundation layer.

2. A bump electrode as claimed in claim 1, wherein a portion of the foundation layer forms a ring laterally extending beyond the base of the bump electrode metal.

3. A bump electrode for connecting a semiconductor device to an external lead by melting a junction metal coating, comprising:

a semiconductor substrate containing the semiconductor device;

a conducting layer formed on the semiconductor substrate having first and second ends, the first end connected to the semiconductor device;

a protection layer formed over the conducting layer having an aperture toward the second end of the conducting layer;

a lower foundation layer of material which does not get wet by the junction metal coating formed on the protection layer over the aperture, the lower foundation film in electrical contact with the conducting layer through the aperture;

an upper foundation layer formed on the lower foundation layer, the lower foundation extending laterally beyond the upper foundation; and

a bump electrode metal formed on the upper and lower foundation layers, the bump electrode metal extending laterally beyond the upper foundation layer and the lower foundation layer extending laterally beyond the bump electrode metal,

whereby the junction metal coating cannot flow past the lower foundation film.

4. A process for manufacturing a bump electrode for connecting a semiconductor device to an external lead by melting a junction metal coating, comprising the steps of:

providing a semiconductor substrate having the semiconductor device formed in the semiconductor substrate;

forming a conductivity layer having first and second ends on the semiconductor substrate so that the first end is in electrical contact with the semiconductor device;

forming a protective layer over the conductivity layer, the protective layer having an aperture toward the second end of the conductivity layer;

forming a foundation layer of material which does not get wet by the junction metal coating over the protective layer and the aperture;

growing a bump electrode metal on the foundation layer, the bump electrode metal having an upper portion laterally extending beyond the lower portion of the bump electrode;

placing a photo resist layer over the foundation layer;

exposing the photo resist layer using the laterally extending upper portion of the bump electrode as a mask; and

etching the foundation layer using the remaining photo resist layer as a mask.

5. A process for manufacturing a bump electrode for connecting a semiconductor device to an external lead by melting a junction metal coating, comprising the steps of:

providing a semiconductor substrate having the semiconductor device formed in the semiconductor substrate;

forming a conductivity layer having first and second ends on the semiconductor substrate so that the first end is in electrical contact with the semiconductor device;

forming a protective layer over the conductivity layer, the protective layer having an aperture toward the second end of the conductivity layer;

forming a lower foundation layer of material which does not get wet by the junction metal coating over the protective layer and the aperture;

forming an upper foundation layer over the lower foundation layer;

placing a photo resist film over the upper foundation layer;

exposing the portion of the photo resist film on the upper foundation layer while masking the portion of the photo resist film covering the aperture;

etching the upper foundation layer using the remaining photo resist film as a mask;

growing a bump electrode metal on the lower foundation layer, the bump electrode metal covering the upper foundation layer and the bump electrode having an upper portion laterally extending beyond the lower portion of the bump electrode;

placing a photo resist layer over the lower foundation layer;

exposing the photo resist layer using the upper portion of the bump electrode as a mask; and

etching the lower foundation layer using the remaining photo resist layer as a mask.